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CD4012BMS Datasheet(PDF) 9 Page - Intersil Corporation

Part # CD4012BMS
Description  CMOS NAND Gates
PDF  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD4012BMS Datasheet(HTML) 9 Page - Intersil Corporation

  CD4012BMS Datasheet HTML 1Page - Intersil Corporation CD4012BMS Datasheet HTML 2Page - Intersil Corporation CD4012BMS Datasheet HTML 3Page - Intersil Corporation CD4012BMS Datasheet HTML 4Page - Intersil Corporation CD4012BMS Datasheet HTML 5Page - Intersil Corporation CD4012BMS Datasheet HTML 6Page - Intersil Corporation CD4012BMS Datasheet HTML 7Page - Intersil Corporation CD4012BMS Datasheet HTML 8Page - Intersil Corporation CD4012BMS Datasheet HTML 9Page - Intersil Corporation  
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7-61
CD4011BMS, CD4012BMS, CD4023BMS
Chip Dimensions and Pad Layouts
FIGURE 7. TYPICAL PROPAGATION DELAY TIME PER GATE
AS A FUNCTION OF LOAD CAPACITANCE
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
CD4011BMSH
CD4012BMSH
CD4023BMSH
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25
oC
10V
15V
SUPPLY VOLTAGE (VDD) = 5V
LOAD CAPACITANCE (CL) (pF)
200
175
150
125
100
75
50
25
0
10
20
30
40
50
60
70
80
90
100
AMBIENT TEMPERATURE (TA) = +25
oC
LOAD CAPACITANCE (CL) (pF)
0
40
60
80
100
20
0
50
100
150
200
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION:
Thickness: 11k
Å
− 14kÅ, AL.
PASSIVATION:
10.4kÅ - 15.6k
Å, Silane
BOND PADS:
0.004 inches X 0.004 inches MIN
DIE THICKNESS:
0.0198 inches - 0.0218 inches



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