323

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

CD4030BMS

Chip Dimensions and Pad Layout

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNC-

TION OF SUPPLY VOLTAGE

FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION AS A

FUNCTION OF INPUT FREQUENCY

SUPPLY VOLTAGE (VDD) (V)

010

15

20

5

100

200

300

LOAD CAPACITANCE (CL) = 50pF

10V

5V

10V

CL = 15pF

CL = 50pF

SUPPLY VOLTAGE

(VDD) = 15V

8

6

4

28

6

4

22

INPUT FREQUENCY (fI) (kHz)

8

6

4

28

6

42

8

6

4

6

4

2

10

1

6

4

2

6

4

2

6

4

2

6

4

2

6

4

2

LOAD CAPACITANCE

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions

METALLIZATION:

Thickness: 11k

Å

PASSIVATION:

10.4kÅ - 15.6k

BOND PADS:

0.004 inches X 0.004 inches MIN

DIE THICKNESS:

0.0198 inches - 0.0218 inches