7-317

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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CD4030BMS

CMOS Quad Exclusive-OR Gate

Pinout

CD4030BMS

TOP VIEW

Functional Diagram

A

B

J = A

⊕ B

K = C

⊕ D

C

D

VSS

VDD

H

G

M = G

⊕ H

L = E

⊕ F

F

E

1

2

3

4

5

6

7

14

13

12

11

10

9

8

J = A

⊕ B

K = C

⊕ D

VSS = 7

VDD = 14

M = G

⊕ H

L = E

⊕ F

1

2

5

6

8

9

12

13

A

B

C

D

E

F

G

H

3

4

10

11

J

K

L

M

Features

• High Voltage Type (20V Rating)

• Medium-Speed Operation

- tPHL, tPLH = 65ns (typ) at VDD = 10V, CL = 50pF

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current Of 1

µA at 18V Over Full

Package-Temperature Range;

• Noise Margin (Over Full Package Temperature Range):

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

• Even and Odd-Parity Generators and Checkers

• Logical Comparators

• Adders/Subtractors

• General Logic Functions

Description

The CD4030BMS types consist of four independent Exclu-

sive-OR gates. The CD4030BMS provides the system

designer with a means for direct implementation of the

Exclusive-OR function.

The CD4030BMS is supplied in these 14-lead outline pack-

ages:

Braze Seal DIP

H4H

Frit Seal DIP

H1B

Ceramic Flatpack H3W

December 1992

File Number

3305