4-99

Setting the Control Register

The following will illustrate a counter write and subsequent

reads that places stable, accurate values on the data bus

from the counter-timer.

The counter is addressed and the required values are

loaded with a write operation. The control register is

addressed next and loaded with B9H.

The counter will now decrement with each input clock pulse

while the gate is valid. Assuming the counter has not decre-

mented to zero and its value is to be read without affecting

the counter’s operation, a write to the control register is per-

formed. 78H is loaded into the control register.

The counter is addressed and read operations are per-

formed.

Function Pin Description

DB7 - DB0 - 8-bit bidirectional bus used to transfer binary

information between the microprocessor and the dual

counter-timer.

A0, A1, and A2 - Addresses used to select counters or reg-

isters.

TPB/WR, RD - Directional signals that determine whether

data will be placed on the bus from a counter or the interrupt

status register (RD active) (memory mapped), or data on the

bus will be placed into a counter or control register (TPB/WR

active). The following connections are required between the

microprocessor and the counter-timer in the CDP1800-

series input/output mapping mode.

During an output instruction, data from the memory is

strobed into the counter-timer during TPB when RD is active,

and latched on TPB’s trailing edge. Data is read from the

counter-timer when RD is not active between the trailing

edges of TPA and TPB. See Figures 11, 12, and 13.

TACL, TBCL - Clocks used to decrement the counter.

TAG, TBG - Gate inputs used to control counter.

TAO, TAO - Complemented outputs of Timer A.

TBO, TBO - Complemented outputs of Timer B.

INT - Common interrupt output. Active when counter decre-

ments to zero.

RESET - Active low signal that resets counter outputs (TAO,

TBO low, TAO, TBO high). The interrupt output is set high

and the status register is cleared.

IO/MEM - Tied high in CDP1800-series input/output mode,

otherwise tied low.

TPA - Tied to TPA of the CDP1800-series microprocessors.

During memory mapping, it is used to latch the high order

address bit for the chip select. In the CDP1800 input/output

mode, it is used to gate the N lines. When the counter-timer

is used with other microprocessors, or when the high order

address of the CDP1800-series microprocessors is exter-

CS - An active high signal that enables the device.

1

0111001

POSITIVE GATE ENABLING

REQUIRED

MODE 1 SELECTED

LOAD COUNTER

HOLDING REGISTER

UPDATED BY COUNTER

COUNTER START

INTERRUPT OUTPUT

ENABLED

CONTROL

REGISTER = B9H

WITH JAM REGISTER

CONTINUOUSLY

BUS 7

BUS 0

FIGURE 6.

0

1111000

COUNTER OUTPUTS

COUNTER VALUE

FREEZE HOLDING

UNCHANGED

CONTROL

REGISTER = 78H

UNAFFECTED

UNAFFECTED

REGISTER

BUS 7

BUS 0

FIGURE 7.

MICROPROCESSOR

COUNTER-TIMER

MRD

RD

TPB

TPB/WR

TPA

TPA

N Lines

Address Lines

CDP1878C