4-132

Signal Descriptions/Pin Functions

CLOCK: Latch Input Control - a high on the clock input will

allow data to pass through the latch to the output pin. Data is

latched on the high-to-low transition of the clock input. This

pin is connected to TPA in CDP1800-series systems and tied

MA0 - MA4: Address inputs to the high-byte address

latches.

MA5 - MA6: High byte address inputs decoded to produce

chip selects CS0 - CS3.

CE: CHIP ENABLE input - A low on this pin will enable the

chip select decoder. A high on this pin forces CS0, CS1,

CS2, and CS3 outputs to a high (false) state.

A8 - A12: Latched high-byte address outputs.

CS0 - CS3: One of four latched and decoded Chip Select

outputs.

Application Information

The CDP1883 and CDP1883C can be interfaced, without

external components, with CDP1800-series microprocessor

systems. These microprocessors feature a multiplexed

address bus and provide an address latch signal (TPA) that

is used as the clock input of the CDP1883. See Figure 2 and

Figure 3.

This signal is used to latch 7 bits of the high-order address.

The lower five high-order address inputs are latched and

held to be used with the eight lower-order address inputs to

access an 8K x 8-bit memory. The two upper high-order

address inputs are latched and decoded for use as chip

selects.

The latched address and decoding functions of the

CDP1883 and CDP1883C allow them to operate with 32K-

byte memory systems. In addition, smaller memory systems

can be configured with 4K x 8-bit or smaller memories, or a

mix of memory sizes up to 8K x 8-bit.

TRUTH TABLE

INPUTS

OUTPUTS

CE

CLK

MA5

MA6

CS0

CS1

CS2

CS3

01000111

01101011

01011101

01111110

0

0

X

X

Previous State

1

X

X

X

1111

TRUTH TABLE

INPUTS

OUTPUTS

CE

CLK

MA0 - 4

A8 - A12

X1

1

1

X1

0

0

X

0

X

Previous State

X = Don’t Care

See Figure 1

PARAMETER

(V)

CDP1883

CDP1883C

UNITS

MIN

(NOTE 1)

TYP

(NOTE 2)

MAX

MIN

(NOTE 1)

TYP

(NOTE 2)

MAX

Minimum Setup Time,

Memory Address to CLOCK

5

-

10

35

-

10

35

ns

10

-

8

25

-

-

-

ns

Minimum Hold Time,

Memory Address After CLOCK

5

-

825

-

825

ns

10

-

8

25

-

-

-

ns

Minimum CLOCK Pulse Width

5

-

50

75

-

50

75

ns

10

-

25

40

-

-

-

ns

PROPAGATION DELAY TIMES

Chip Enable to Chip Select

5

-

75

150

-

75

150

ns

10

-

45

100

-

-

-

ns

CLOCK to Chip Select

5

-

100

175

-

100

175

ns

10

-

65

125

-

-

-

ns

CDP1883, CDP1883C