FRE9160R datasheet(2/6 Pages) INTERSIL

2 / 6 page

Pre-Radiation Electrical Speciﬁcations TC = +25oC, Unless Otherwise Speciﬁed

PARAMETER

SYMBOL

TEST CONDITIONS

LIMITS

UNITS

MIN

MAX

Drain-Source Breakdown Volts

BVDSS

VGS = 0, ID = 1mA

-100

Gate-Threshold Volts

VGS(th)

VDS = VGS, ID = 1mA

-2.0

-4.0

Gate-Body Leakage Forward

IGSSF

VGS = -20V

100

Gate-Body Leakage Reverse

IGSSR

VGS = +20V

100

Zero-Gate Voltage

Drain Current

IDSS1

IDSS2

IDSS3

VDS = -100V, VGS = 0

VDS = -80V, VGS = 0

VDS = -80V, VGS = 0, TC = +125oC

0.025

0.25

Rated Avalanche Current

IAR

Time = 20

µs

Drain-Source On-State Volts

VDS(on)

VGS = -10V, ID = 30A

-2.99

Drain-Source On Resistance

RDS(on)

VGS = -10V, ID = 19A

0.095

Ω

Turn-On Delay Time

td(on)

VDD = -50V, ID = 30A

Rise Time

Pulse Width = 3

µs

440

Turn-Off Delay Time

td(off)

Period = 300

µs, Rg = 10Ω

250

Fall Time

≤ VGS ≤ 10 (See Test Circuit)

170

Gate-Charge Threshold

QG(th)

VDD = -50V, ID = 30A

IGS1 = IGS2

≤ VGS ≤ 20

418

Gate-Charge On State

QG(on)

350

Gate-Charge Total

QGM

180

750

Plateau Voltage

VGP

-3

-14

Gate-Charge Source

QGS

Gate-Charge Drain

QGD

140

Diode Forward Voltage

VSD

ID = 30A, VGD = 0

-0.6

-1.8

Reverse Recovery Time

I = 30A; di/dt = 100A/

µs

400

Junction-To-Case

θjc

0.83

oC/W

Junction-To-Ambient

θja

Free Air Operation

FIGURE 1. RESISTIVE SWITCHING TEST CIRCUIT

FIGURE 2. UNCLAMPED ENERGY TEST CIRCUIT

VDD

VDS

DUT

RGS

VGS = -12V

VGS ≤ 20V

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

Ω

50V-150V

IAS

ELECTRONIC SWITCH OPENS

WHEN IAS IS REACHED

CURRENT

TRANSFORMER

FRE9160D, FRE9160R, FRE9160H

FRE9160R Datasheet(PDF) 2 Page - Intersil Corporation

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