ADE7569_15 datasheet(101/152 Pages) AD

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 101 of 152

Table 89. LCD Configuration X SFR (LCDCONX, Address 0x9C)

Bit

Mnemonic

Default

Description

Reserved

Reserved.

EXTRES

External resistor ladder selection bit.

EXTRES

Result

External resistor ladder is disabled. Charge pump is enabled.

External resistor ladder is enabled. Charge pump is disabled.

[5:0]

BIASLV

Bias level selection bits. See Table 90.1

1 This feature is not available in the ADE7116.

Table 90. LCD Bias Voltage When Contrast Control Is Enabled1

BIASLVL[5]

VA (V)

1/2 Bias

1/3 Bias

[ ]

BLVL

REF

VB = VA

VC = 2 × VA

VB = 2 × VA

VC = 3 × VA

[ ]

⎟

⎠

⎞

⎜

⎝

⎛ +

BLVL

REF

VB = VA

VC = 2 × VA

VB = 2 × VA

VC = 3 × VA

1 This feature is not available in the ADE7116.

Table 91. LCD Configuration Y SFR (LCDCONY, Address 0xB1)

Bit

Mnemonic

Default

Description

Reserved

This bit should be kept cleared for proper operation.

INV_LVL

Frame inversion mode enable bit. If this bit is set, frames are inverted every other frame. If this bit is

cleared, frames are not inverted.

[5:2]

Reserved

0000

These bits should be kept cleared to 0 for proper operation.

UPDATEOVER

Update finished flag bit. This bit is updated by the LCD driver. When set, this bit indicates that the

LCD memory has been updated and a new frame has begun.

REFRESH

Refresh LCD data memory bit. This bit should be set by the user. When set, the LCD driver does not

use the data in the LCD data registers to update the display. The LCD data registers can be updated

by the 8052. When cleared, the LCD driver uses the data in the LCD data registers to update display

at the next frame.

Table 92. LCD Clock SFR (LCDCLK, Address 0x96)

Bit

Mnemonic

Default

Description

[7:6]

BLKMOD

Blink mode clock source configuration bits.

BLKMOD

Result

The blink rate is controlled by software; the display is off.

The blink rate is controlled by software; the display is on.

The blink rate is 2 Hz.

The blink rate is set by BLKFREQ.

[5:4]

BLKFREQ

Blink rate configuration bits. These bits control the LCD blink rate if the BLKMOD bits = 11.

BLKFREQ

Result (Blink Rate)

1 Hz

1/2 Hz

1/3 Hz

1/4 Hz

[3:0]

LCD frame rate selection bits. See Table 93 and Table 94.

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