ADE7569_15 datasheet(104/152 Pages) AD

104 / 152 page

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 104 of 1

The LCD waveform frequency, fLCD, is the frequency at which

the LCD switches the active common line. Thus, the LCD

waveform frequency depends heavily on the multiplex level.

The frame rate and LCD waveform frequency are set by fLCDCLK,

the multiplex level, and the FD[3:0] frame rate selection bits in

the LCD clock SFR (LCDCLK, Address 0x96).

The LCD module provides 16 different frame rates for

fLCDCLK = 2048 Hz, ranging from 8 Hz to 128 Hz for an LCD

with 4× multiplexing. Fewer options are available with

fLCDCLK = 128 Hz, ranging from 8 Hz to 32 Hz for a 4× multi-

plexed LCD. The 128 Hz clock is beneficial for battery

operation because it consumes less power than the 2048 Hz

clock. The frame rate is set by the FD bits in the LCD clock

SFR (LCDCLK, Address 0x96); see Table 93 and Table 94.

The LCD waveform is inverted at twice the LCD waveform

frequency, fLCD. This way, each frame has an average dc offset

of 0. ADC offset degrades the lifetime and performance of

the LCD.

BLINK MODE

Blink mode is enabled by setting the BLINKEN bit (Bit 5) in the

LCD Configuration SFR (LCDCON, Address 0x95). This mode

is used to alternate between the LCD on state and LCD off state

so that the LCD screen appears to blink. There are two blinking

modes: a software controlled blink mode and an automatic

blink mode.

Software Controlled Blink Mode

The LCD blink rate can be controlled by user code with the

BLKMOD bits in the LCD clock SFR (LCDCLK, Address 0x96)

by toggling the bits to turn the display on and off at a rate

determined by the MCU code.

Automatic Blink Mode

There are five blink rates available if the RTC peripheral is

enabled. These blink rates are selected by the BLKMOD and

BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96);

see Table 92.

DISPLAY ELEMENT CONTROL

A bank of 15 bytes of data memory located in the LCD module

controls the on or off state of each segment of the LCD. The

LCD data memory is stored in Address 0 through Address 14 in

the LCD module. Each byte configures the on and off states of two

segment lines. The LSBs store the state of the even numbered

segment lines, and the MSBs store the state of the odd numbered

segment lines. For example, LCD Data Address 0 refers to

Segment Line 1 and Segment Line 0 (see Table 99). Note that the

LCD data memory is maintained in the PSM2 operating mode.

The LCD data memory is accessed indirectly through the LCD

pointer SFR (LCDPTR, Address 0xAC) and LCD Data SFR

(LCDDAT, Address 0xAE). Moving a value to the LCDPTR SFR

selects the LCD data byte to be accessed and initiates a read or

write operation (see Table 96).

Writing to LCD Data Registers

To update the LCD data memory, first set the LSB of the LCD

Configuration Y SFR (LCDCONY, Address 0xB1) to freeze the

data being displayed on the LCD while updating it. This

operation ensures that the data displayed on the screen does not

change while the data is being changed. Then, move the data to

the LCD data SFR (LCDDAT, Address 0xAE) prior to accessing

the LCD pointer SFR (LCDPTR, Address 0xAC). When the

MSB of the LCD pointer SFR (LCDPTR, Address 0xAC) is set,

the content of the LCD data SFR (LCDDAT, Address 0xAE) is

transferred to the internal LCD data memory designated by the

address in the LCDPTR SFR. Clear the LSB of the LCD

Configuration Y SFR (LCDCONY, Address 0xB1) when all of

the data memory has been updated to allow the use of the new

LCD setup for display.

Sample 8052 code to update the segments attached to FP10 and

FP11 pins, use the following sample 8052 code:

ORL

LCDCONY,#01h

;start updating the data

MOV

LCDDAT,#FFh

MOV

LCDPTR,#80h OR 05h

ANL

LCDCONY,#0FEh ;update finished

Reading LCD Data Registers

When the MSB of the LCD Pointer SFR (LCDPTR, Address

0xAC) is cleared, the content of the LCD data memory address

designated by LCDPTR is transferred to the LCD data SFR

(LCDDAT, Address 0xAE).

Sample 8052 code to read the contents of LCD Data Memory

Address 0x07, which holds the on and off state of the segments

attached to FP14 and FP15, is as follows.

MOV

LCDPTR,#07h

MOV

R1, LCDDAT

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