ADE7762_15 datasheet(5/28 Pages) AD

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ADE7762

Rev. 0 | Page 5 of 28

Parameter

Conditions

Min

Typ

Max

Unit

POWER SUPPLY

For specified performance

VDD

5 V ± 5%

4.75

5.25

IDD

8.5

1 See the Terminology section for explanation of specifications.

2 See the plots in the Typical Performance Characteristics section.

3 Sample tested during initial release and after any redesign or process changes that might affect this parameter.

TIMING CHARACTERISTICS

VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.

Table 2.

Parameter1,2

Conditions

Value

Unit

t1 3

F1 and F2 pulse width (logic high)

120

Output pulse period (see the Transfer Function section)

See Figure 2

sec

Time between F1 rising edge and F2 rising edge

½ t2

sec

t43, 4

CF pulse width (logic high)

t55

CF pulse period (see the Transfer Function section)

See Table 7

sec

Minimum time between F1 and F2 pulse

4/CLKIN

sec

LED_CTRL pulse width

28.8

μs

LED_CTRL period

57.5

μs

LED pulse width

7.2

μs

1 Sample tested during initial release and after any redesign or process changes that might affect this parameter.

2 See Figure 2.

3 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies (see the Frequency Outputs section).

4 CF is not synchronous to F1 or F2 frequency outputs.

5 The CF pulse is always 1 μs in the high frequency mode (see the Frequency Outputs section).

Figure 2. Timing Diagram for Frequency Outputs

Figure 3. Timing Diagram for LED Drivers

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