2

Simplified Block Diagram

Pin Descriptions

+

-

GATE

CTIM

PGOOD

PWRON

CLIM

WOCLIM

ENABLE

OC

10

µA

FALLING

EDGE

DELAY

18V

+

-

+

-

1.86V

12V

+

-

R

R

S

QN

Q

ENABLE

POR

8V

RISING

EDGE

PULSE

+

-

+

-

UV

18V

20

µA

7.5k

+

-

+

-

10

µA

PIN #

SYMBOL

FUNCTION

DESCRIPTION

1

ISET

Current Set

Connect to the low side of the current sense resistor through the current limiting set resistor.

This pin functions as the current limit programming pin.

2

ISEN

Current Sense

Connect to the more positive end of sense resistor to measure the voltage drop across this

resistor

3

GATE

External FET Gate Drive

Pin

Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground

4

VSS

Chip Return

Chip Supply

12V chip supply. This can be either connected directly to the +12V rail supplying the switched

6

CTIM

Current Limit Timing

Capacitor

Connect a capacitor from this pin to ground. This capacitor determines the time delay

between an overcurrent event and chip output shutdown (current limit time-out). The duration

of current limit time-out (in seconds) = 93k

7

PGOOD

Power Good Indicator

Indicates that the voltage on ISEN pin is within specification. PGOOD is driven by an open

drain N-Channel MOSFET and is pulled low when the output is not within specification.

8

PWRON

Power ON

PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven

high or is open. After a current limit time out, the chip is reset by a low level signal applied to

this pin. This input has 20

µA pull up capability

HIP1015, HIP1016