HIP6007 datasheet(7/10 Pages) INTERSIL

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Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectiﬁed buck converter. The output voltage

(Vout) is regulated to the Reference voltage level. The error

ampliﬁer (Error Amp) output (VE/A) is compared with the

oscillator (OSC) triangular wave to provide a pulse-width

modulated (PWM) wave with an amplitude of Vin at the

PHASE node. The PWM wave is smoothed by the output

ﬁlter (Lo and Co).

The modulator transfer function is the small-signal transfer

function of Vout/VE/A. This function is dominated by a DC

Gain and the output ﬁlter (Lo and Co), with a double pole

break frequency at FLC and a zero at FESR. The DC Gain of

the modulator is simply the input voltage (Vin) divided by the

peak-to-peak oscillator voltage

∆VOSC.

Modulator Break Frequency Equations

The compensation network consists of the error ampliﬁer

(internal to the HIP6007) and the impedance networks ZIN

and ZFB. The goal of the compensation network is to provide

a closed loop transfer function with the highest 0dB crossing

frequency (f0dB) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f0dB and

180o

. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 8. Use these guidelines for

locating the poles and zeros of the compensation network:

Compensation Break Frequency Equations

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1ST Zero Below Filter’s Double Pole

(~75% FLC)

3. Place 2ND Zero at Filter’s Double Pole

4. Place 1ST Pole at the ESR Zero

5. Place 2ND Pole at Half the Switching Frequency

6. Check Gain against Error Ampliﬁer’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Figure 8 shows an asymptotic plot of the DC-DC converter’s

gain vs frequency. The actual Modulator Gain has a high gain

peak do to the high Q factor of the output filter and is not

shown in Figure 8. Using the above guidelines should give a

Compensation Gain similar to the curve plotted. The open

loop error amplifier gain bounds the compensation gain.

Check the compensation gain at FP2 with the capabilities of

the error amplifier. The Closed Loop Gain is constructed on

the log-log graph of Figure 8 by adding the Modulator Gain (in

dB) to the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the

compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks

ZFB and ZIN to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45o.

Include worst case component variations when determining

phase margin.

FIGURE 7. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

VOUT

OSC

REFERENCE

ESR

VIN

∆VOSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

REF

COMP

VOUT

ZFB

HIP6007

ZIN

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

VE/A

ZIN

ZFB

LC =

•

---------------------------------------

ESR =

ESR

•

()

•

--------------------------------------------

Z1 =

π R2 C1

•

---------------------------------

P1 =

π R2

•

C1 + C2

----------------------





•

------------------------------------------------------

Z2 =

R1 + R3

()

•

-----------------------------------------------------

P2 =

π R3

•

---------------------------------

100

-20

-40

-60

FP1

FZ2

10M

100K

10K

100

OPEN LOOP

ERROR AMP GAIN

FZ1

FP2

FLC

FESR

COMPENSATION

FREQUENCY (Hz)

GAIN

20LOG

(VIN/∆VOSC)

MODULATOR

GAIN

20LOG

(R2/R1)

CLOSED LOOP

GAIN

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

HIP6007

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