HIP7010 datasheet(9/20 Pages) INTERSIL

9 / 20 page

Bus Arbitration

The nature of multiplexed communications leads to contention

issues when two or more nodes attempt to transmit on the bus

simultaneously. Within J1850 VPW systems, messages are

assigned varying levels of priority which allows implementa-

tion of an arbitration scheme to resolve potential contentions.

The speciﬁed arbitration is performed on a symbol by symbol

basis throughout the duration of every message.

Arbitration begins with the rising edge of the SOF pulse. No

node should attempt to issue an SOF until an Idle bus has

been detected (i.e., an

Inter-Frame Separation (IFS) symbol

with a period of TV6 has been received). If multiple nodes are

ready to access the bus and are all waiting for an IFS to

elapse, invariable skews in timing components will cause one

arbitrary node to detect the Idle condition before all others and

start transmission ﬁrst. For this reason, all nodes waiting for

an IFS will consider an IFS to have occurred if either:

1. An IFS nominal period has elapsed

2. An EOF minimum period has elapsed

and a rising edge

has been detected

Arbitrating devices will all be synchronized during the SOF.

Beginning with the ﬁrst data bit and continuing to the EOF,

every transmitting device is responsible for verifying that the

symbol it sent was the symbol which appeared on the bus.

Each transition, every transmitting node must decode the

symbol, verify the received symbol matches the one sent, and

begin timing of the next symbol. Since timing of the next sym-

bol begins with the last transition detected on the bus, all

transmitters are re-synchronized each symbol. When the

received symbol doesn’t match the symbol sent, a conﬂict (

bit

collision) occurs. Any device detecting a collision will assume

it has lost arbitration and immediately relinquish the bus. Typi-

cally, after losing arbitration, a device will attempt retransmis-

sion of the message when the bus once again becomes idle.

The deﬁnition of 1 and 0 data bits (see Table 2 and discussion

under VPW Symbol Deﬁnitions) leads to 0’s having priority

over 1’s in this arbitration scheme. Header bytes are generally

assigned such that arbitration is completed before the ﬁrst

data byte is transmitted. Because of the dominance of 0 bits

and the MSB ﬁrst bit order, a header with the hexadecimal

value $00 will have highest priority, then $01, $02, $03, etc.

An example of two nodes arbitrating for control of the bus is

shown in Figure 6.

Arbitration also takes place during the IFR portion of a mes-

sage, if more than one node is attempting to generate a

response. Arbitration begins with the NB symbol, which fol-

lows the EOD and precedes the ﬁrst IFR byte.

For Type 1 and Type 3 messages only, the respondent which

successfully arbitrates for control of the bus produces an IFR.

All other respondents abort their IFRs.

For Type 2 messages, all respondents which lose arbitration

must re-attempt transmission at the end of each byte. Each

node, which successfully responds, eliminates itself from the

subsequent arbitration until all nodes have responded. This

arbitration scheme limits each respondent to a single byte dur-

ing a Type 2 IFR.

Break

To force a message to be aborted before EOF is reached, a

break (BRK) symbol can be transmitted by any node. The

BRK symbol is an active pulse of duration TV5. Reception of a

break causes all nodes to reset to a

ready-to-receive state

and to re-arbitrate for control following an IFS.

HIP7010 Architectural Overview

The HIP7010 consists of three major functional blocks: the

Serial Interface System (SERIAL) block; the State Machine

(STATE) block; and the Symbol Encoder/Decoder (SENDEC)

block. Transfers between the Host and the HIP7010 are con-

trolled by the SERIAL block, while transfers between the

J1850 bus and the HIP7010 are handled by the SENDEC

FIGURE 5. J1850 MESSAGE WITH IN-FRAME-RESPONSE

FIGURE 6. TWO NODES ARBITRATING FOR CONTROL OF J1850 BUS

SOF

HEADER

. . . . DATA N

CRC

IN FRAME RESPONSE

EOD

EOF

SOF

000

HEADER

COLLISION DETECTED BY B

J1850

TRANSMITTER

DATA 1 . . . DATA N

CRC

EOF

IFS

BUS

HIP7010

HIP7010 Datasheet(PDF) 9 Page - Intersil Corporation

HIP7010 Datasheet(HTML) 9 Page - Intersil Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL