HIP7010 datasheet(12/20 Pages) INTERSIL

12 / 20 page

B5, 0

Bit 5 of the Status byte is not used and will always

read as a 0.

B4, FTU

When First Time Up (FTU) is high, it indicates

that a reset has occurred since the last Sta-

tus/Control Register transfer. FTU is high during

the ﬁrst Status/Control Register transfer after a

reset and low thereafter.

FTU can be used to recognize that a Slow Clock

Detect reset has occurred or to ensure that a Sta-

tus/Control Register transfer has been success-

fully completed since the last reset.

B3, 4X

The 4X status ﬂag indicates that the 4X mode bit

has been set in the Control Register. This bit

reﬂects the contents of the Control Register not

the current mode of the HIP7010’s SENDEC. The

SENDEC only changes modes synchronously

with an edge detected on the VPWIN pin. See

description of the 4X control bit for details. 4X is

cleared by reset and the trailing edge of a break.

B2, CRC The CRC Error ﬂag (CRC) is set when a CRC

error has been detected in the current frame.

CRC is cleared by reset and at the conclusion of

the Status/Control Register transfer.

B1, ERR The Error ﬂag (ERR) is set when an illegal symbol

or other, non-CRC error has been detected on the

VPWIN pin. Following are some of the many errors

which will cause ERR to be set: 1. An illegal sym-

bol, (i.e., a symbol other than a TV1, TV2, or Break

in the middle of a data byte); 2. Receipt of a trun-

cated byte (i.e., less than 8 symbols); 3. The Host

attempting to initiate a message more than 96

µs

after the IDLE line goes high; 4. An improperly

framed message (i.e., SOF not equal to TV3,

wrong EOD, EOF, or NB widths); 5. Failure by the

Host to use the long form of RDY to indicate the

last byte of a message; 6. An attempt by the Host

to transmit a single byte (Type 1 or Type 2) IFR by

setting ACK but without using the long form of RDY

for the byte transfer; 7. Setting the Host asserting

STAT during a data byte transfer; 8. A transition

has occurred on the VPWOUT pin and the

reﬂected transition has not been detected on

VPWIN (echo fail).

ERR is cleared by a reset and at the conclusion

of the Status/Control Register transfer.

B0, BRK

The break ﬂag (BRK) is set on the ﬁrst rising edge

of VPWIN after a BRK symbol has been detected

on the J1850 bus. If the Host was transmitting or

has a message to transmit, it should re-arbitrate

for the bus following an IFS (IDLE goes low).

BRK automatically clears the 4X mode of the SEN-

DEC and resets the 4X bit in the Status byte.

BRK is cleared by a reset or at the conclusion of

the Status/Control Register transfer.

Control Register

The Control Register contains eight, write-only, control bits.

The PD, NXT, MACK, and ACK bits can only be set high;

they are cleared by hardware under speciﬁc conditions. The

other four bits can be both set and reset by the Host. All bits

in the Control Register are cleared by reset.

B7, ACK

Setting the Acknowledgment (ACK) bit signals the

HIP7010

that,

following

the

EOD,

IFR

response is to be sent. Once set, the ACK bit can-

not be cleared by the Host. ACK is cleared upon

successful transmission of the IFR or at the next

Idle.

The ACK bit can be set anytime prior to 135

µs

after the ﬁnal byte (the CRC) of a message. The

ﬁrst IFR byte must be loaded into the Host’s serial

output register, and the RDY line set after the

HIP7010 transfers the next-to-last byte to the

Host, and before the HIP7010 transfers the last

byte (CRC) of the J1850 message to the Host.

When the CRC byte is sent to the Host from the

HIP7010, the IFR byte will be simultaneously

loaded into the HIP7010.

To send a single byte (Type 1 or Type 2) IFR the

Host must leave MACK (B6 of the Control Regis-

ter) low and use the long RDY line format.

When sending a single byte (Type 1 or Type 2)

IFR, the possibility of losing arbitration exists. In

the case of a Type 1 IFR no further action should

be taken. The standard protocol for handling loss

of arbitration during a Type 2 IFR is to re-attempt

the transmission until successful. To ensure

proper transmission of the IFR the Host must

repeatedly load it’s serial output register with the

desired IFR byte, and set RDY (using the short

format), until the IFR has been properly received

back. There is no danger of inadvertently sending

the IFR byte twice. The HIP7010 monitors the

arbitration results and will transmit the IFR byte

only once. The ACK bit is automatically cleared

upon the ﬁrst successful transmission, thus pre-

venting a second transmission. The Host controls

when the ACK bit is set. During normal operation

the Host must only set ACK once per IFR.

To send a Type 3 IFR the Host must set MACK

high and use the short format of the RDY for all

bytes except the last, when the long format is

used. A CRC will automatically be appended to

the last byte of a Type 3 IFR. A Type 3 IFR, con-

sisting of a single byte plus CRC, can be created

by setting MACK high and using the long RDY line

format for loading the single data byte.

When sending a Type 3 IFR, the possibility of los-

ing arbitration during the IFR also exists. In the

case of Type 3 IFRs, once arbitration has been

765

ACK

MACK

NXT

DS2

DS1

DS0

HIP7010

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