7-71

Control Interface

The QPSK modulator is configured via a serial three wire

interface. When C_EN is high, 23 bits are shifted in at the

CDATA pin on the falling edge of CCLK. Figure 3 shows the

timing diagram for loading the serial configuration data.

Table 1 describes the 23-bit serial configuration data. See

the Synthesizer Section for more details on the frequency

control bits.

Synthesizer

The

synthesizer

generates

the

quadrature

LO’s

for

modulating the baseband data to RF. The carrier frequency

is phase locked to the reference clock (RCLK). The carrier

with a resolution of 32kHz. Equation 1 gives the relationship

control bits, M and A.

can be determined by

“A” ranges from 0 to 5 and “M” ranges from 41 to 103. A and

M are programmed via control bits D0-D2 and D3-D9,

respectively. Values outside these ranges are invalid.

I/Q Generator

The I/Q Generator Section demultiplexes and time aligns the

256 KBPS input data into two data streams, I and Q. The

first data bit following the assertion of the TX_EN signal is

the I data of the first I/Q pair. Each I/Q pair determines the

phase angle of the QPSK transmission signal. The relation-

ship between I/Q pairs and phase angles is shown in

Table 2. Since the QPSK encoding requires a pair of I and Q

information to transmit one symbol, an even number of data

bits must be provided for each burst.

TABLE 1. 23-BIT SERIAL DATA CONTROL INTERFACE

DESCRIPTION

BIT

POSITION

FUNCTION

DESCRIPTION

D0-D2

(Note)

Synthesizer

Control Bits

Pre-scaler control register.

A = (0 to 5), D2 is the MSB.

D3-D9

Synthesizer

Control Bits

Feedback Counter Control Register.

M = (41 to 103) D9 is the MSB.

D10

Synthesizer

Enable

Active high. This bit activates chip bias

networks for normal operation. D10 = 0

places part in low power mode.

D11

Charge Pump

Current

Control

D11 = 0 sets charge pump current to

500

µA.

D11 = 1 sets charge pump current to

1mA.

D12

Three-State

Control

D12 = 0 three-states the charge pump

output when a pump up and down

command

occur

simultaneously.

D12 = 1 disables three-state.

D13-D18

Attenuation

Control

Controls output power level. The bina-

ry value of the register corresponds to

an attenuation amount. For example,

000100 corresponds to 4dB attenua-

tion from the maximum 62dBmV level.

D18 is the MSB.

D19-D21

Reserved

Used for test/diagnostic purposes.

Set to 000.

D22

DSP Shut

Down

Test mode; D22 = 0 sets the burst

QPSK modulator in normal mode.

D22 = 1 disables the digital filter.

NOTE: D0 is the first bit shifted into the part.

TABLE 2. QPSK ENCODING

I

Q

PHASE

00

0

1

1

0

1

1

F

6M

1

+

() A

+

64

---------------------------------

F

(EQ. 1)

M

A

6

----

+

64

6

------

F

C

F

REF

---------------

1.

–

=

(EQ. 2)

CCLK

C_DATA

C_EN

D22

D2

D1

D0

D19

D20

D21

D3

FIGURE 3. CONTROL INTERFACE TIMING DIAGRAM

HSP50307