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W9812G2KB Datasheet(PDF) 6 Page - Winbond

Part # W9812G2KB
Description  1M X 4 BANKS X 32 BITS SDRAM
PDF  43 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W9812G2KB Datasheet(HTML) 6 Page - Winbond

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W9812G2KB
Publication Release Date: Jun. 20, 2014
- 6 -
Revision: A01
5.
BALL DESCRIPTION
BALL NUMBER
SYMBOL
FUNCTION
DESCRIPTION
G8,G9,F7,F3,G1,G2,
G3,H1,H2,J3,G7,H9
A0
A11
Address
Multiplexed pins for row and column address.
Row address: A0
A11. Column address: A0A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
J7,H8
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
R8,N7,R9,N8,P9,M8
,M7,L8,L2,M3,M2,P1
,N2,R1,N3,R2,E8,D7
,D8,B9,C8,A9,C7,A8
,A2,C3,A1,C2,B1,D2
,D3,E2
DQ0
DQ31
Data
Input/ Output
Multiplexed pins for data output and input.
J8
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is ignored
and previous operation continues.
J9
RAS
Row Address
Strobe
Command input. When sampled at the rising edge
of the clock
RAS , CAS and WE define the
operation to be executed.
K7
CAS
Column Address
Strobe
Referred to RAS
K8
WE
Write Enable
Referred to RAS
K9,K1,F8,F2
DQM0~3
Input/Output
mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with
zero latency.
J1
CLK
Clock Inputs
System clock used to sample inputs on the rising edge of
clock.
J2
CKE
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
A7,F9,L7,R7
VDD
Power
Power for input buffers and logic circuit inside DRAM.
A3,F1,L3,R3
VSS
Ground
Ground for input buffers and logic circuit inside DRAM.
B2,B7,C9,D9,E1,L1,
M9,N9,P2,P7
VDDQ
Power for I/O
buffer
Separated power from VDD, to improve DQ noise
immunity.
B8,B3,C1,D1,E9,L9,
M1,N1,P3,P8
VSSQ
Ground for I/O
buffer
Separated ground from VSS, to improve DQ noise
immunity.
E3,E7,H3,H7,K2,K3
NC
No Connection
No connection



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