11

Propagation Delay

The converter requires two clock rising edges for data to be

represented at the output. Each rising edge of the clock

captures the present data word and outputs the previous

data. The propagation delay is therefore 1/CLK, plus <2ns of

processing. See Figure 15.

Test Service

Intersil offers customer-specific testing of CommLink

converters with a service called Testdrive. To submit a

request, fill out the Testdrive form. The form can be found by

doing an ‘entire site search’ at www.intersil.com on the

words ‘DAC Testdrive’. Or, send a request to the technical

support center.

FIGURE 13. OUTPUT LOADING FOR DATASHEET

MEASUREMENTS

PIN 21

PIN 22

ISL5761

IOUTB

IOUTA

L

OAD SEEN BY THE TRANSFORMER

1:1

AT EACH OUTPUT

FIGURE 14. ALTERNATIVE OUTPUT LOADING

PIN 21

PIN 22

ISL5761

IOUTB

IOUTA

AT EACH OUTPUT

LOAD SEEN BY THE TRANSFORMER

Timing Diagram

FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM

CLK

50%

D9-D0

ISL5761