8

Byte Format

Every byte put on the SDA line must be 8-bits long. The

number of bytes that can be transmitted per transfer is

unrestricted. Each byte has to be followed by an acknowledge

bit. Data is transferred with the most significant bit first (MSB).

Acknowledge

The master (microprocessor) puts a resistive HIGH level on

the SDA line during the acknowledge clock pulse (Figure 3).

The peripheral that acknowledges has to pull down (LOW)

the SDA line during the acknowledge clock pulse, so that the

SDA line is stable LOW during this clock pulse. (Of course,

set-up and hold times must also be taken into account.)

The peripheral which has been addressed has to generate

an acknowledge after the reception of each byte, otherwise

the SDA line remains at the HIGH level during the ninth

clock pulse time. In this case, the master transmitter can

generate the STOP information in order to abort the transfer.

The ISL6421 will not generate the acknowledge if the

POWER OK signal from the UVLO is LOW.

Transmission Without Acknowledge

Avoiding detection of the acknowledgement, the

microprocessor can use a simpler transmission; it waits one

clock without checking the slave acknowledging, and sends

the new data.

This approach, though, is less protected from error and

decreases the noise immunity.

ISL6421 Software Description

Interface Protocol

The interface protocol is comprised of the following, as

shown below in Table 2:

• A start condition (S)

• A chip address byte (MSB on left; the LSB bit determines

address for the ISL6421 is 0001 00XX)

• A sequence of data (1 byte + Acknowledge)

• A stop condition (P)

When the R/W bit in the chip is set to 0, the main

microprocessor can write on the system register (SR1) of the

microprocessor as shown below.

SDA

SCL

1

2

8

9

ACKNOWLEDGE

FROM SLAVE

MSB

START

TABLE 2. INTERFACE PROTOCOL

S 000 1000 R/W ACK Data (8 bits) ACK P

TABLE 3. SYSTEM REGISTER 1 (SR1)

R, W

R, W

R, W

R, W

R, W

R, W

R, W

R

SR1

DCL

X

ENT1

LLC1

VSEL1

EN1

OLF1

TABLE 4. SYSTEM REGISTER 2 (SR2)

R, W

R, W

R, W

R, W

R, W

R, W

R

R

SR2

X

X

X

X

EN2

OTF

X

System Register Format

All bits reset to 0 at Power-On

TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION

SR

DCL

ISEL1

ENT1

LLC1

VSEL1

EN1

OLF1

FUNCTION

0

1

0

0

1

SR1 is selected

0

1

0

0

1

Vout1 = 13V, Vboost1 = 13V + Vdrop

0

1

0

1

1

Vout1 = 18V, Vboost1 = 18V + Vdrop

0

1

1

0

1

Vout1 = 14V, Vboost1 = 14V + Vdrop

0

1

1

1

1

Vout1 = 19V, Vboost1 = 19V + Vdrop

0

1

0

1

22kHz tone is controlled by the DSQIN pin

0

1

1

1

22kHz tone is ON, the DSQIN input is disabled

ISL6421