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ADV601LC

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DRAM Interface Pins

Name

Pins

I/O

Description

DDAT[15:0]

I/O

DRAM Data Bus. The ADV601LC uses these pins for 16-bit data read/write

operations to the external 256K

× 16-bit DRAM. (The operation of the DRAM

interface is fully automatic and controlled by internal functionality of the

ADV601LC.) These pins are compatible with 30 pF loads.

DADR[8:0]

DRAM Address Bus. The ADV601LC uses these pins to form the multiplexed

row/column address lines to the external DRAM. (The operation of the DRAM

interface is fully automatic and controlled by internal functionality of the

ADV601LC.) These pins are compatible with 30 pF loads.

RAS

DRAM Row Address Strobe. This pin is compatible with 30 pF loads.

CAS

DRAM Column Address Strobe. This pin is compatible with 30 pF loads.

DRAM Write Enable. This pin is compatible with 30 pF loads.

Note that the ADV601LC does not have a DRAM OE pin. Tie the DRAM’s

OE pin to ground.

Host Interface Pins

Name

Pins

I/O

Description

DATA[31:0]

I/O

Host Data Bus. These pins make up a 32-bit wide host data bus. The host

controls this asynchronous bus with the WR, RD, BE, and CS pins to commu-

nicate with the ADV601LC. These pins are compatible with 30 pF loads.

ADR[1:0]

Host DWord Address Bus. These two address pins let you address the

ADV601LC’s four directly addressable host interface registers. For an illustra-

tion of how this addressing works, see the Control and Write Register Map

figure and Status and Read Register Map figure. The ADR bits permit register

addressing as follows:

ADR1

ADR0

DWord

Address Byte Address

0x00

0x04

0x08

0x0C

BE0–BE3

Host Word Enable pins. These two input pins select the words that the

ADV601LC’s direct and indirect registers access through the Host Interface;

BE0–BE1 access the least significant word, and BE2–BE3 access the most

significant word. For a 32-bit interface only, tie these pins to ground, making

all words available.

Some important notes for 16-bit interfaces are as follows:

•

When using these byte enable pins, the byte order is always the lowest byte

•

to the higher bytes.

•

The ADV601LC advances to the next 32-bit compressed data FIFO location

•

after the BE2–BE3 pin is asserted then de-asserted (when accessing the Com-

•

pressed Data register); so the FIFO location only advances when and if the

•

host reads or writes the MSW of a FIFO location.

•

The ADV601LC advances to the next 16-bit indirect register after the BE0–BE1

•

pin is asserted then de-asserted; so the register selection only advances when

•

and if the host reads or writes the MSW of a 16-bit indirect register.

Host Chip Select. This pin operates as follows:

•

LO Qualifies Host Interface control signals

•

HI Three-states DATA[31:0] pins

Host Write. Host register writes occur on the rising edge of this signal.

Host Read. Host register reads occur on the low true level of this signal.

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