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ALUC1900B2 Datasheet(PDF) 3 Page - Advanced Semiconductor Business Inc. |
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ALUC1900B2 Datasheet(HTML) 3 Page - Advanced Semiconductor Business Inc. |
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3 / 3 page ![]() 3/3 www.asb.co.kr January 2010 plerowTM ALUC1900B2 Internally Matched Balanced LNA Module Including Coupler 1) The tantal or MLC (Multi Layer Ceramic) capacitor is optional and for bypassing the AC noise introduced from the DC supply. The capacitance value may be determined by customer’s DC supply status. The ca- pacitor should be placed as close as possible to Vs pin and be connected directly to the ground plane for the best electrical performance. 2) DC blocking capacitors are always necessarily placed at the input and output port for allowing only the RF signal to pass and blocking the DC component in the signal. The DC blocking capacitors are includ- ed inside the ALUC module. Therefore, C1 & C2 capacitors may not be necessary, but can be added just in case that the customer wants. The value of C1 & C2 is determined by considering the application fre- quency. Application Circuit Recommended Soldering Reflow Process 20~40 sec 260 C 200 C 150 C 60~180 sec Ramp-up (3 ˚C/sec) Ramp-down (6 C/sec) IN OUT Vs Size 40x40 mm (for ALUC Series – 22x12 mm) Evaluation Board Layout VS Tantal or MLC (Multi Layer Ceramic) Capacitor ALUC OUT IN C1 C2 + - + - Tantal or MLC (Multi Layer Ceramic) Capacitor VS Vs |
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