UPD17010 datasheet(13/424 Pages) NEC

13 / 424 page

µPD17010

Pin No.

Symbol

Function

Output Format

Power-ON Reset

Selects operation of

µPD17010 and inputs reset

—

Input

signal.

(1) Device operation selection

The PLL frequency synthesizer can operate

while CE pin is high.

When CE pin is low, the PLL frequency

synthesizer is automatically disabled

(operation inhibited) internally.

(2) Reset signal input

When CE pin goes high, device is reset in

synchronization with internal basic timer 0

carry FF (CE reset).

This pin does not accept high or low level of

less than 110 to 165

µs to prevent malfunction-

ing due to noise.

Input signal level of this pin can be detected by

CEJDG register (address 07H) of register file.

At this time, contents of CEJDG register are

not changed by low or high level of less than

110 to 165

µs. This pin is Schmitt trigger input

pin with hysteresis.

Exercise care that voltage higher than VDD is

not applied to this pin on power application.

If voltage higher than VDD is applied,

µPD17010 may not operate correctly.

P1A3

I/O of port 1A and input of external gate counter.

CMOS push-pull

Input

• P1A3-P1A0

(P1A3-P1A0)

P1A1

• 4-bit CMOS I/O port

P1A0/FCG

• Can be set in input or output mode in 1-bit units

• FCG

• Input to frequency counter for external gate

P1B3/PWM2Note

Port 1B, and output of D/A converter and clock

N-ch open-drain

Outputs undefined

P1B2/PWM1Note

generator port.

Withstanding 16 V

data (P1B3-P1B0)

P1B1/PWM0Note

• P1B3-P1B0

P1B3-PWM2

P1B0/CGP

• 4-bit output port

• PWM2-PWM0

P1B1-PWM0

• Output of D/A converter with 8-bit resolution

CMOS

• CGP

push-pull

• Clock generator port output

(P1B0-CGP)

P1C3

4-bit CMOS output port

CMOS

Outputs undefined

push-pull

data

P1C0

Note

The P1B3/PWM2 through P1B1/PWM0 are N-ch open-drain output pins and must be connected with external

pull-up resistors.

UPD17010 Datasheet(PDF) 13 Page - NEC

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