UPD17016 datasheet(13/324 Pages) NEC

13 / 324 page

µPD17016, 17017

Pin No.

Symbol

Function

Output Form

On Power-ON Reset

Selects operation of

µPD17017 and inputs reset signal.

–

Input

(1)

Device operation selection

PLL frequency synthesizer can operate when CE

pin is high; it is automatically disabled (operation

prohibited) while CE pin is low.

(2)

Reset signal input

When CE pin goes high, device is reset in

synchronization with internal basic timer 0 carry FF

(CE reset).

This pin does not accept low or high level of less

than 110 to 165

µs to prevent malfunctioning due to

noise.

Input signal level of this pin can be detected by CE

pin level judge register of register file (address

07H).

Contents of CE pin level judge register are not

changed by low or high level of less than 110 to

165

µs. This pin is a Schmitt trigger input pin with

hysteresis characteristics.

Do not apply voltage higher than VDD to this

pin on power application; otherwise, normal

operation will not be performed.

P1A3

4-bit CMOS I/O port.

CMOS

Input

Can be set in input or output mode in 1-bit units.

push-pull

P1A0

P1B3Note

Port 1B also serving as D/A converter and buzzer output pins.

N-ch

Outpus

P1B2/PWM1Note

• P1B3-P1B0

open drain,

undefined data

P1B1/PWM0Note

• 4-bit output port

16 V

(P1B3-P1-B0)

P1B0/BEEP

• PWM1, PWM0

P1B3,

• D/A converter output with 8-bit resolution

P1B2/PWM1,

• BEEP

P1B1/PWM0

• Buzzer output

CMOS

push-pull

(P1B0/BEEP)

P1C3

4-bit CMOS output port.

CMOS

Outputs

push-pull

undefined data

P1C0

Note

The P1B3, P1B2/PWM1, and P1B1/PWM0 pins are N-ch open-drain output pins and must be connected to

an external pull-up resistor.

UPD17016 Datasheet(PDF) 13 Page - NEC

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