AN4253 datasheet(22/44 Pages) STMICROELECTRONICS

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HW resource initialization

AN4253

22/44

DocID024255 Rev 2

If the startup relies on a code execution from the core, there is no need to change the

configuration of the AIPS. But when the startup wants to use DMA capability, it is necessary

to change MPROT.MPL bit field.

Code sequence

Write value 0x77770070 to AIPS_MPROT register

7.2

PFlash controller setup

PFlash controller acts as an interface between masters (AHB bus) and a Flash memory

array. It controls timing access time and buffering scheme for instruction fetches and data

read.

Figure 11. PFlash controller

7.2.1

Default reset configuration

Default setting is optimal for startup code execution that will run on 120 MHz clock. An

assumption is that the startup code does not use many constants placed in Flash as data

buffer is disabled.

Note:

PFlash register modification shall be done when executing the code from RAM

7.2.2

Code sequence

No need to change default reset configuration.

7.3

Core registers initialization

When running the Leopard device in Lock-Step mode (LSM) it is important to initialize some

of the Core registers to a value that are identical for both Cores. The reason behind this is

that some Core registers are un-initialized by the reset and it can happen that under certain

•

Instruction fetch

Buffers enabled (3x for instruction fetch), prefetch enabled

•

Data read

Buffer disabled

•

Access timing

3 wait states

AN4253 Datasheet(PDF) 22 Page - STMicroelectronics