AN4253 datasheet(26/44 Pages) STMICROELECTRONICS

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HW resource initialization

AN4253

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DocID024255 Rev 2

Configure input clock to FMPLL0

External crystal oscillator shall be used as input to FMPLL block. A selection is done in the

AUX_Clock selector 3 block.

Default reset value

Code sequence

Set SELCTL bit field of CGM_AC3_SC register to 1 (XOSC)

Configure FMPLL0

The FMPLL0 configuration consists in setting right values to, IDF, ODF and NDIV, in

FMPLL0.CR register. Values have to fulfill equations given in RM0032 (see B.1: Reference

documents). Their values depend on selected crystal oscillator and target system frequency.

Default reset values

Example 1

Setting for 120 MHz system clock derived from 40 MHz crystal oscillator

Code sequence

Write IDF,ODF and NDIV values to FMPLL0.CR register

(0xC3FE_00A0)

Enable FMPLL0 block (mode transition)

It is necessary to set PLL0ON bit in ME_DRUN_MC register and then to initiate a mode

transition to DRUN.

Code sequence

Set bit PLL0ON in ME_DRUN_MC register

Write DRUN with Key_1 in ME_MCTL register

Write DRUN with Key_2 in ME_MCTL register

Wait mode transition to finish (ME_GS.MTRANS bit = 0)

•

FMPLL0 input

IRC_16 MHz. It is necessary to change it to XOSC.

•

IDF=1

Input frequency divided by 2. It must be changed to fulfill 4-16 MHz input

range in case of 40 MHz crystal oscillator

•

ODF=1

Divide VCO output frequency by 4.

•

NDIV=64

Input frequency divided by IDF block multiplied by NDIV to get VCO

frequency, which must be within 256-512 MHz frequency range.

•

IDF=3

40 MHz / 4 = 10 MHz as input to FMPLL

•

NDIV=48

10 MHz * 48 = 480 MHz as VCO frequency

•

ODF=1

480 MHz / 4 = 120 MHz system clock

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