DocID025336 Rev 1

11/23

AN4370

Diagnostic

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Diagnostic

Diagnostic information is classified in different categories: Functional Errors (FE), Device

Errors (DE), Fail Safe errors (FS) and Global Warnings (GW).

Once entered in FS condition due to a detected FS event, all the control registers are write

protected, except the following bits: WDG trigger & GOSTBY/STBYSEL, which allow

sending the device in one of the two possible STDBY modes, even though the device is in

FS condition. In Fail Safe condition the following features will be disabled and all the control

registers, except Control Register 1 and DSFT_DIS bit, will be reset to default values. These

are the blocks disabled in Fail Safe condition: CP, BEMFIP, CSA & GATE DRIVERS

(actively discharged before disabling them). Some events detected by default as faults

could be programmed just to trigger warnings instead. This latter option can be

controlled/modified by SPI. An error flag, except NRDY (automatically cleared), can be

cleared only if the related fault condition ended before the reception of the related R&C

command; otherwise the flag will not be cleared. Since the NRDY flag will automatically be

cleared as soon as the VCP, right after a POR, rises above the VCPLOW threshold, it could

happen that a reading command of the content of SR1, that includes the NRDY flag,

received while the NRDY flag is being automatically cancelled, returns the following wrong

temporary reading of the status register (SR1):0800h for CPLOWM = 1 or 0200h for

CPLOWM = 0 (of course assuming the NRDY flag the only one responsible for a GSB value

different than 80h. In fact the expected value returned by a reading command should be

0840h or 0240h respectively). After this temporary wrong value read any further reading

command of SR1 will return to its correct value, which is 8000h.

It is important to know that the device supports bitwise Read and Clear operations for each

status register. This means that a R&C operation can be addressed to specific status flags.

For instance to clear just the DISABLE status flag (BIT5) of Status Register 1, the

microcontroller should send the following binary code to achieve the desired effect without

clearing any other flag of the same register:

Figure 5. SPI command frame structure (SDI)