AN3392 datasheet(22/57 Pages) STMICROELECTRONICS

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Voltage regulation

AN3392

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Doc ID 018749 Rev 1

Voltage regulation

In order to protect both the device itself and the load, the SPV1020 implements a dual

control of the output voltage (VOUT).

Control of VOUT is done through the VOUT_SNS pin, connected to VOUT by a resistive divider

(see Section 10 for resistance values). The control consists of comparing VOUT_SNS with

two internal thresholds:

1.00 V, for voltage regulation

1.04 V, for overvoltage protection.

When VOUT_SNS increases up to 1 V, the output feedback loop enters regulation, limiting the

output voltage. Regulation is achieved by creating an upper limit for the DC generated by the

MPPT algorithm.

The stability of the loop must be externally compensated by connecting a resistor and a

capacitor (pole-zero combination) between the PZ_OUT pin and SGND pin (see Section 10

for values).

7.1

Overvoltage protection

If the VOUT_SNS exceeds 1.04 V, a fault signal is generated and transmitted to the fault

controller which stops the drivers and produces a fault, setting the bit OVV in the status

command (op code 0x07). When VOUT_SNS drops back down to 1.04 V the DC-DC

converter is switched ON again and the converter restarts the MPP search from the

minimum duty cycle (5 %).

7.2

Overcurrent protection

To guarantee the safety of the entire application, the SPV1020 implements an overcurrent

protection on the low-side power switches. In fact, when Lx is accidentally shorted to Vin or

VOUT, or when the current flowing through the inductor exceeds the peak current limit

(4.5 A), the related low-side power switch is immediately turned OFF and the linked

synchronous rectifier is enabled to turn on. The low-side power switch is turned on again at

the next PWM cycle.

In the case of overcurrent on branch x [x = 1..4], the related OVC bit of the status register is

set. This information is accessible through the SPI interface by the Read Status command

(op code 0x07).

7.3

Current balance

Different parasitic resistances between the four branches of the IL-4 architecture can be the

root cause of unbalanced current flow between the four branches. This should be avoided

as it may result in lower efficiency or damage to external components (inductors) and/or the

SPV1020.

It is recommended that the four branches in the PCB layout have symmetrical paths and the

inductors be matching or from the same production lot.

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