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AN1059 Datasheet(PDF) 17 Page - STMicroelectronics |
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AN1059 Datasheet(HTML) 17 Page - STMicroelectronics |
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17 / 20 page ![]() mm air gap 90 primary turns will result in about 970 µH primary inductance. 14 secondary turns give a 6.43 turns ratio, very close to the target. Estimating the thermal resistance of the ETD29 equal to 26°C/W, the maximum power dissipation (supposed to be on copper only) for 30°C hot-spot temperature rise will be 1.15W (half will be allocated to the primary and half to the secondary). This requires the resistance of the primary to be no more than 1.26 Ω and the secondary’s no more than 40 m Ω. An AWG27 (∅ ≈ 0.4 mm) wire for the primary and a strand of 5xAWG27 for the secondary will meet the requirement.The primary winding will be split in two halves of 45 turns each, series connected, and the secondary will be sandwiched in be- tween to reduce leakage inductance. 6. MOSFET selection - Maximum Drain Voltage:VDSmax = VPKmax + VR + ∆V = 373 + 100 + 70 = 543V There is margin to select a 600 V device. This will minimise gate drive and capacitive losses. Assuming that the MOSFET will dissipate 5% of the input power, that losses are due to con- duction only, and that RDS(on) doubles at working temperature, the RDS(on) at 25°C should be about 2 Ω. An STP4NA60 (RDS(on) = 2.2 Ω max.) is selected. 7. Catch diode selection - Maximum reverse voltage: VREVmax = VPKmax n + Vout = 373 6.41 + 15 = 73.2V A 100V Schottky diode will minimise conduction losses. As to its current rating, a tentative value can be 40% of the peak current: IF = 0.4 ⋅ IPKs = 0.4 ⋅ 13.1 = 5.2A. A suitable device could be the STPS8H100D. From the relevant datasheet, the power dissipation is estimated as: Pdiode = 0.48 ⋅ Iout + 0.013 ⋅ IRMSs 2 = 0.55 ⋅ 2 + 0.013 ⋅ 3.792 = 1.15W, which is acceptable. 8. Output Capacitor Selection The minimum capacitance value that meets the specification on the 100/120 Hz ripple is: Coutmin = 1 π ⋅ fL ⋅ H2 (Kv) F2 (kv) ⋅ Iout ∆Vo = 0.108 ⋅ 2 3.14 ⋅ 50 ⋅ 0.254 ⋅ 1 = 5417µF Three 2200 µF electrolytic capacitors will have an ESR low enough to consider the high fre- quency ripple negligible as well as sufficient AC current capability. 9. Clamp network With a proper construction technique, the leakage inductance can be reduced to as much as 2% of the primary inductance, that is 20 µH in the present case. A transil clamp is selected. The clamp voltage will be VCL = VR + ∆V = 100 + 70 = 170V. The steady-state power dissipa- tion is estimated to be about 2W. A P6KE170A transil is selected. The blocking diode is an STTA106. 10. Multiplier bias and sense resistor selection Assuming a peak value of 2.4V (@VAC = 264V) on the multiplier input (MULT, pin 3), the peak value at minimum line voltage will be VMULTpkmin = 2.4 ⋅ 88/264 = 0.8V which, multiplied by the maximum slope of the multiplier, 1.65, gives 1.32V peak voltage on current sense (CS, pin 4). Since the linearity limit (1.6V) is not exceeded, this is acceptable. The divider ratio will then be 2.4/( √2 ⋅ 264) = 6.43 ⋅ 10-3. Considering 120µA current for the divider, the lower resistor will be 20k Ω, and the upper one 3MΩ.The sense resistor will not exceed 1.32/2.32 = 0.57Ω (0.5Ω is selected), while its power rating will be 0.5 ⋅ IRMSp 2 = 0.5 ⋅ 0.6752 = 228mW 11. Feedback and Control Loop The selected optocoupler is a 4N35 from Toshiba. 1 mA quiescent collector current is se- lected. From opto’s datasheet, with 1mA collector current, the diode current can be between 1 and 2 mA approximately (0.5 < CTR < 1). AN1059 APPLICATION NOTE 17/20 |
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