1.2MHz (see fig 4). When the oscillator output is at ground , C3 is charged by Vs through D1. When it

rises to 10V, D1 is reverse biased and the charge flows from C3 to C4 through D2, so the Vboot pin af-

ter a few cycles reaches the maximum voltage of Vs + 10V - VD1- VD2.

Vboot ( BOOTSTRAP).

This is the input bootstrap pin which gives the overvoltage necessary to drive all the upper DMOS of the

three half bridges (see fig 5).

LOGIC INPUTS PINS.

EN1, EN2, EN3 (ENABLES).

These pins are TTL/CMOS and

µP compatible. Each half bridge can be enabled by its own dedicated

pin with a logic HIGH. The logic LOW on these pins switches off the related half bridge (see Fig. 6). The

maximum switching frequency is 50kHz.

IN1, IN2, IN3 (INPUTS).

These pins are TTL/CMOS and

µP compatible. They allow switching on the upper DMOS ( INPUT at

high logic level) or the lower Dmos (INPUT at low logic level) in each half bridge (see Fig. 6).

10nF

VCP

1N4148

0.22

VBOOT

1N4148

CHARGE

PUMP

Vref

10V

0.1

Vs

100

HIGH

SIDE

DRIVER

Vs+Vref-VD1-VD2

Vref

f=1.2 MHz

Vs+Vref-VD1

Vs-VD1

f=1.2 MHz

D1

D2

C3

C4

C2

C1

OUT

Vs

SENSE

Figure 5. Charge Pump Circuit.

UPPER

DMOS

LOWER

DMOS

DMOS ON

DMOS OFF

DMOS ON

time

time

DMOS OFF

ENABLE

high level

low level

time

DMOS OFF

INPUT

time

high level

low level

low level

high level

high level

DMOS OFF

low level

DMOS OFF

DMOS OFF

Figure 6. Control logic for each half bridge.

tdelay

300ns

tdelay

300ns

INPUT

PIN

UPPER

DMOS

LOWER

DMOS

high level

low level

DMOS ON

DMOS OFF

DMOS ON

DMOS OFF

time

time

time

DMOS OFF

DMOS ON

low level

Figure 7. Cross Conduction Protection.

AN1088 APPLICATION NOTE

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