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AN1517 Datasheet(PDF) 14 Page - STMicroelectronics |
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AN1517 Datasheet(HTML) 14 Page - STMicroelectronics |
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14 / 30 page ![]() Closing the loop AN1517 14/30 DocID8827 Rev 3 Equation 13 Where K is equal to 0.076. Therefore the PWM gain is also equal to: Equation 14 This means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, thus ensuring a better line regulation and line transient response. To sum up, the open loop gain can be written as: Equation 15 Example 1 Considering RC = 2.7 k, CC = 22 nF and CP = 220 pF, the poles and zeroes of A0 are: FP1 = 9 Hz FP2 = 256 kHz FZ1 = 2.68 kHz If L = 22 µH, COUT = 100 µF and ESR = 80 m, the poles and zeroes of ALC become: FPLC = 3.39 kHz F0 = 19.89 kHz Finally R1 = 5.6 k and R2 = 3.3 k. The gain and phase bode diagrams are plotted respectively in Figure 11 and Figure 12. Figure 11. Module plot VOSCMAX VOSCMIN – KVCC = GPWM s 1 K ---- const == Gs GPWM s R2 R1 R2 + -------------------- AO s ALC s = |
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