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AN2335 Datasheet(PDF) 23 Page - STMicroelectronics

Part # AN2335
Description  This document is intended to give application
PDF  40 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN2335 Datasheet(HTML) 23 Page - STMicroelectronics

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AN2335
Data and status registers
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ZOR is set to 1 whenever a new acceleration sample related to the Z-axis is generated
before the retrieval of the previous sample. When this occurs the previous sample is
overwritten. ZOR is cleared anytime OUTZ register is read.
YOR is set to 1 whenever a new acceleration sample related to the Y-axis is generated
before the retrieval of the previous sample. When this occurs the previous sample is
overwritten. YOR is cleared anytime OUTY_H register is read.
XOR is set to 1 whenever a new acceleration sample related to the X-axis is generated
before the retrieval of the previous sample. When this occurs the previous sample is
overwritten. XOR is cleared anytime OUTX_H register is read.
The ZYXDA bit signals that a new sample for all the enabled channels is available. ZYXDA
is cleared when the acceleration data (OUTX, OUTY, OUTZ) of all the enabled channels are
read.
ZDA is set to 1 whenever a new acceleration sample related to the Z-axis is available. ZDA
is cleared anytime OUTZ register is read. In order to trigger, the ZDA bit requires the Z axis
to be enabled (bit Zen=1 inside CTRL_REG1).
YDA is set to 1 whenever a new acceleration sample related to the Y-axis is available. YDA
is cleared anytime OUTY register is read. In order to trigger, the YDA bit requires the Y axis
to be enabled (bit Yen=1 inside CTRL_REG1).
XDA is set to 1 whenever a new acceleration sample related to the X-axis is available. XDA
is cleared anytime OUTX register is read. In order to trigger, the XDA bit requires the X axis
to be enabled (bit Xen=1 inside CTRL_REG1).
7.3
OUTX (29h)
X-axis output register.
7.4
OUTY (2Bh)
Y-axis output register.
.
7.5
OUTZ (2Dh)
Z-axis output register.
.
XD7
XD6
XD5
XD4
XD3
XD2
XD1
XD0
YD7
YD6
YD5
YD4
YD3
YD2
YD1
YD0
ZD7
ZD6
ZD5
ZD4
ZD3
ZD2
ZD1
ZD0



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