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AN2335 Datasheet(PDF) 31 Page - STMicroelectronics

Part # AN2335
Description  This document is intended to give application
PDF  40 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN2335 Datasheet(HTML) 31 Page - STMicroelectronics

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AN2335
Application Information
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9
Application Information
9.1
START-UP SEQUENCE
Once the device is powered-up it automatically downloads the calibration coefficients from
the embedded flash to the internal registers. When the boot procedure is completed, i.e.
approximately after 3 milli-seconds, the device automatically enters power-down mode.
To turn-on the device and gather acceleration data it is necessary to write 47h inside the
CTRL_REG1. With this command the three acceleration channels (i.e. X, Y and Z axis) are
enabled and the Output Data Rate is set to 100 Hz.
9.2
READING ACCELERATION DATA
9.2.1
Using the Status Register
The device is provided with a STATUS_REG which should be polled to check when a new
set of data is available. The reading procedure should be the following:
The check performed at step 3 allows to understand whether the reading rate is adequate
compared to the data production rate. In case one or more acceleration samples have been
overwritten by new data because of a reading rate too slow, the bit STATUS_REG(7) will be
set to 1.
The overrun bit are automatically cleared when all the data present inside the device have
been read and new data have not been produced in the meanwhile.
9.2.2
Using the Data-Ready Signal
The device may be configured to generate one HW signal (Data Ready) on either pin 8 or 9
to flag that a new set of measurement data is available for reading. This signal corresponds
to the ZYXDA bit present inside the STATUS_REG. The polarity of the signal is defined
through the IHL bit present inside the CTRL_REG3 and it is deasserted when the
acceleration data of all the enabled channels have been read. To enable Data Ready signal
on pin #8 (corresponding to INT1) it is necessary to set I1CFG[2:0] bit present inside the
CTRL_REG3 to 100. Conversely, to enable Data Ready signal on pin #9 (corresponding to
INT2) it is necessary to set I2CFG[2:0] bit present inside the CTRL_REG3 to 100.
1
read STATUS_REG
2
if STATUS_REG(3)=0 then goto 1
3
if STATUS_REG(7)=1 then some data have been overwritten
4
read OUTX
5
read OUTY
6
read OUTZ
7
data processing
8
goto 1



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