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UPD17933 Datasheet(PDF) 39 Page - NEC |
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UPD17933 Datasheet(HTML) 39 Page - NEC |
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39 / 252 page ![]() 39 µPD17933, 17934 5.3 Address Register (AR) 5.3.1 Configuration of address register Figure 5-3 shows the configuration of the address register. As shown in the figure, the address register consists of 16 bits of system register addresses 74H through 77H (AR3 through AR0). Figure 5-3. Configuration of Address Register Address Name Symbol Bit Data 74H AR3 75H AR2 76H AR1 77H AR0 b3 M S B b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 L S B Reset by RESET pin WDT&SP reset Clock stop Address register (AR) 0 0 Retained 0 0 Retained 0 0 Retained 0 0 Retained Reset by RESET pin WDT&SP reset Clock stop : Reset by RESET pin : Reset by watchdog timer and stack pointer : On execution of clock stop instruction |
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