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UPD17933 Datasheet(PDF) 13 Page - NEC |
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UPD17933 Datasheet(HTML) 13 Page - NEC |
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13 / 252 page ![]() 13 µPD17933, 17934 Pin No. Symbol Function Output Form 40 COM0 These pins output the common signals of the LCD controller/driver. CMOS | | At reset On clock stop 3-state 43 COM3 Reset by RESET pin WDT&SP reset Output low level Output low level Output low level 44 LCD0 These pins are the segment signal output pins of the LCD controller/driver. CMOS | | push-pull 60 LCD16 61 P2A0/LCD17 Port 2A input port, the segment signal output pins of the LCD controller/driver. – | P2A1/LCD18 • P2A0 through P2A2 63 P2A2/LCD19 3-bit input port • LCD17 through LCD19 LCD segment output At reset On clock stop Reset by RESET pin WDT&SP reset Input (P2A2-P2A0) Input (P2A2-P2A0) Retained 64 P0C0 4-bit output CMOS | | At reset On clock stop push-pull 67 P0C3 Reset by RESET pin WDT&SP reset Output low level Output low level Retained 68 INT Edge-detected vector interrupt input. – Rising or falling edge is selectable. 69 XOUT Crystal resonator connection pin. – 70 XIN 71 P2C0 These pins form a 4-bit I/O port which can be set in the input or output mode CMOS | | in 1-bit units. push-pull 74 P2C3 At reset On clock stop Reset by RESET pin WDT&SP reset Input Input Retained 75 P0D0 Port 0D input port, A/D converter input pins and to release the HALT – | P0D1/AD0 and STOP modes. 78 P0D2/AD1 • P0D0 through P0D3 P0D3/AD2 4-bit input port • AD0 through AD2 Analog input of A/D converter • HALT and STOP mode releasing Releases HALT or STOP mode when a high level is input. At reset On clock stop Reset by RESET pin WDT&SP reset Input with pull-down resistor Input with pull-down resistor Retained (P0D3-P0D0) (P0D3-P0D0) |
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