AN3142 datasheet(22/44 Pages) STMICROELECTRONICS

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Designing a fixed-off-time PFC

AN3142

22/44

Doc ID 17005 Rev 3

Pin 2 (COMP): This pin is the output of the E/A that is fed into one of the two inputs of the

multiplier. A feedback compensation network is placed between this pin and INV (pin#1). It

must be designed with a narrow bandwidth in order to avoid the system rejecting the output

voltage ripple (100 Hz) that would bring high distortion of the input current waveform. A

theoretical criterion to define the compensation network value is to set the E/A bandwidth

(BW) from 20 to 30 Hz.

For a more complex way of compensating the FOT PFC please refer to [

1], [2], [3].

A compensated two-pole feedback network for this 400 W FOT PFC is obtained with the

following values:

to which the following open-loop transfer function and its phase function correspond.

The two bode plot charts are in reference to the PFC operating at the main voltage set point

of 265 VAC and full load. In this condition the crossover frequency is fc = 4 Hz, the phase

margin is 50° and the third harmonic distortion is under 3%.

Pin 4 (CS): Pin #4 is the inverting input of the current sense comparator. Through this pin,

the L6563S reads the instantaneous inductor current, converted in a proportional voltage by

an external sense resistor (Rs). As this signal crosses the threshold set by the multiplier

output, the PWM latch is reset and the power MOSFET is turned off. The MOSFET stays in

OFF-state until the PWM latch is set again by the ZCD signal. The pin is equipped with 150

ns leading-edge blanking for improved noise immunity.

The sense resistor value (Rs) can be calculated as follows. For the 400 W PFC it is:

Equation 44

100

compP =

compS

Ω

compS

(14)

Figure 12.

Open-loop transfer function-bode

plot

Figure 13.

Phase

-200

-100

100

0. 1

100

1000

f [Hz]

-200

-150

-100

0.1

100

1000

f [Hz]

max

min

Vcs

Ω

124

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