PM0222 datasheet(22/33 Pages) STMICROELECTRONICS

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Timers

PM0222

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M0 side (see Section 4: Interrupt management). To initiate the IP there are three important

registers:



WDT_LR: which contains the value to load in the timer (when this register is written, the

counter is immediately restarted from the new value)



WDT_CR: which configures the action to process in case the WDG timer reaches zero

(generation of an interrupt or a reset)



WDT_ICR: writing to this register will clear the watchdog interrupt and reload the

counter from the WDT_LR register.

8.3

SysTick

The Cortex-M0 in Brain provides a SysTick timer. See Brain reference manual, System

timer chapter for more details.

The SysTick timer is clocked by the CPU clock.

All SysTick registers are available through a structure defined in core_cm0.h (Cortex-M0

header provided by ARM). This example will use this set of registers to configure the Systick

with the biggest value and launch it:

Disable the SysTick and the previous configuration (in case of previous use):

SysTick->CTRL= 0x0; // stop the SysTick timer

In this example the SysTick is initialized with the maximum value:

SysTick->LOAD= 0x0FFFFFF; // load value in the SysTick timer

After 16777215 tick periods the counter will reach the targeted value in the LOAD register.

Then enable the counter on the CPU clock:

0x1 | 0x1 << 1 | 0x1 << 2; // enable the counter, enable the interrupt and select the

processor clock

The VAL register contains the current value of the SysTick counter. A read from this register

returns the number of tick periods since the timer has been launched (note that when the

counter reaches the targeted value, it restarts):

current = SysTick->VAL; // save the SysTick timer value

PM0222 Datasheet(PDF) 22 Page - STMicroelectronics