PM0222 datasheet(25/33 Pages) STMICROELECTRONICS

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PM0222

I2C

All I²C registers are described in a structure defined in the Brain header file (.h) provided by

STMicroelectronics. Each I²C can operate in master or slave mode, up to 400 kHz (fast

mode). Standard mode is also supported up to 100 kHz.

Brain has two I²C available at the following addresses in the memory map:



I2C2 APB base address: 0xA400_0000



I2C1 APB base address: 0xA500_0000

10.1

I2C FIFO management

The transmit and receive paths are buffered with internal FIFO memory enabling up to 16

bytes to be stored independently in both transmit and receive modes.

FIFOs status can be checked using the I²C interrupts. There is a programmable threshold

value for each FIFO. When the number of entries is greater for the receive FIFO or less for

the transmit FIFO, an interrupt is set.

10.2

I2C clock rate calculation example

To define the I²C clock rate generation there is one register to configure: I2C_BRCR.

The clock rate can be calculated using this formula:

Clock rate = FI2CCLK / ( (BRCNT2 x 2) + Foncycle ) ) (standard mode)

Clock rate = FI2CCLK / ( (BRCNT2 x 3) + Foncycle ) ) (fast mode)

where:



FI2CCLK is the I²C reference clock frequency, clocked on the system clock divided by

three



BRCNT2 is a field of the I2C_BRCR register



Foncycle depends on a programmable field of the I2C_CR register:

I2C_CR: FON = “00” => Filter the clock spike wide = 0 => Foncycle = 1

I2C_CR: FON = “01” => Filter the clock spike wide = 1 => Foncycle = 3

I2C_CR: FON = “10” => Filter the clock spike wide = 2 => Foncycle = 4

I2C_CR: FON = “11” => Filter the clock spike wide = 4 => Foncycle = 6

Example: programming a clock rate

If the system clock is the RC80Mhz: FI2CCLK = 26.66 MHz and we need a 300 kHz I²C

clock rate without font cycle in fast mode.

According to the previous equation in fast mode: 0.300 = 26.66 / ((BRCNT2 x 3) + 1)

BRCNT2 = (26.66 – 0.3) / 0.9 = 29.2 = 0x1D

This equation provides a theoretical value. The baud rate actually generated on the master

clock line may differ due to the charge on the I2C bus or due to the bounding choice (open-

drain or push-pull I/Os).

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