8/17

MIGRATING APPLICATIONS FROM ST72511/311/314/124 TO ST72521/321/324

4.4 WATCHDOG TIMINGS

In the ST72521/321R, 321/324J, the watchdog timeout does not have an exact duration like in

the ST72511/311R, 314N, 314/124J. It may vary between the min. and max. times specified in

Figure 2. To guarantee upward compatibility, you have to take this into account when you de-

velop your software. The reason for this change is that the watchdog counter has been

grouped with the Active-HALT counter and SLOW mode prescaler to enhance power con-

sumption and EMC performance.

Figure 1. Watchdog Block Diagram

In the ST72521/321R, 321/324J datasheet, the linear relationship between the 7-bit value to

be loaded in the Watchdog Counter (CNT) and the resulting timeout duration in milliseconds is

described. This can be used for a quick calculation without taking the timing variations into ac-

count. If more precision is needed, use the formulae in Figure 2

.

RESET

WDGA

7-BIT DOWNCOUNTER (CNT)

T6

T0

WDG PRESCALER

WATCHDOG CONTROL REGISTER (WDGCR)

DIV 4

T1

T2

T3

T4

T5

12-BIT MCC

RTC COUNTER

MSB

LSB

DIV 64

0

5

6

11

MCC/RTC

TB[1:0] bits

(MCCSR

Register)