14/17

MIGRATING APPLICATIONS FROM ST72511/311/314/124 TO ST72521/321/324

In the ST72521/321R, 321/324J PWM mode, any new values written in the four OC1R and

OC2R registers are taken into account only at the end of the PWM period (OC2 event) to avoid

spikes on the PWM output.

Note: Any modification on the OC1R and OC2R registers must be done just after the OC2

event (using the ICF1 interrupt routine for example).

7.1.2 One Pulse Mode

To be used more efficiently, the One Pulse mode sequence of the ST72511/311R, 314N, 314/

124J has been improved in the ST72521/321R, 321/324J. When the ICAP1 event occurs (on

falling or rising edge) the following sequence occurs:

– 1. IC1R is loaded with the value of the counter when the event occurred (not FFFDh as in

the ST72511/311R, 314N, 314/124J)

– 2. The counter is immediately reset to FFFCh (not at the end like in the ST72511/311R,

314N, 314/124J)

– 3. OLVL2 is applied to OCMP1 pin if OC1E=1

– 4. ICF1 is set

7.1.3 ST72324J Timer A Limitations

If the Timer A IC2/OC2 functions are required when migrating from ST72314/124J then you

should migrate to the ST72321J. Timer A on the ST72324 only has one IC and one OC func-

tion. This has the following impact on the application software:

– The OC2HR and OC2LR registers are reserved (see Note 2).

– The IC2HR and IC2LR registers are reserved (see Note 2).

– The FOLV2 and OLVL2 i control bits in the CR1 register must be kept cleared.

– The OC2E and IEDG2 control bits in the CR2 register must be kept cleared.

– The ICF2 and OCF2 flags must always be masked (meaningless).

– The PWM generated by timer A has a frequency given only by the timer overflow value

(FFFFh) and the prescaler ratio selected by the CR2 CC[1:0] control bits.

Notes:

1. Migration from the ST72314 to the ST72324 must take into account the discrepancy in Tim-

er A functionality between these two devices.

2. A dummy read to the OC2LR and IC2LR registers has to be performed at the end of the

Timer A interrupt routine.

7.2 SPI

7.2.1 Baud Rate