Device ruggedness

AN1256

4/7

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Device ruggedness

The SD2933 is very rugged. Most DMOS failures during operating conditions are due to the

inability to support the effective drain voltage across the body-drain pn junction during an

overvoltage condition when, for example, a mismatched load causes a large voltage

standing wave on the drain terminal. If the device is subjected to an excessive drain to

source voltage, the electric field across this junction reaches a critical value at which point

avalanche current is generated. Under these conditions, current flows from the source to the

body, effectively biasing the internal parasitic bipolar transistor to an on-state, creating a

catastrophic failure very quickly. The voltage required to turn on the parasitic transistor has a

negative temperature coefficient, thus at higher operating temperatures this phenomena is

more likely. It can be noted that some manufacturers of high power RF devices do not

specify a load mismatch, but the SD2933 is guaranteed to sustain a 5:1 load mismatch

across all phase angles with no degradation in output power when returned to 50 ohms.

This load mismatch is comparable to devices with similar output power levels utilizing a

push-pull package configuration. The ability of the SD2933 to handle such a severe

mismatch can be attributed to two design improvements over similar devices. The first being

a proprietary doping scheme of the transistor die during its fabrication process, which allows

high current and voltage swings without inducing turn-on of the internal parasitic bipolar

transistor, and the second enhancement is the lower thermal resistance of the packaging

allowing for increased power dissipation of the device. These considerations result in a very

high breakdown voltage minimum rating of 125 V, with a normal distribution of 145 V DC.

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Design considerations

Designing the SD2933 offered two distinct challenges beyond the semiconductor device

design; one was due to the high gain of the SD2933 in the HF frequency band, and the other

was due to the high power dissipation of this single ended device. The gfs of this device is

very high thus, stabilizing the transistor was extremely critical. Without the use of any

stabilization technique, the device would oscillate and destroy itself under bias conditions

before the RF input was applied. To overcome potential instabilities, gate resistors were

employed. These resistors, as mentioned before, are eutectically mounted inside the

package along with the transistor die and are wired in series with each gate pad. This layout

presents a series resistance to each gate site and thus any difference between the site to

site impedances are small relative to the total.