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PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7MC

5.3 EXAMPLE OF CONFIGURATION OF THE ST7MC REGISTERS

As explained in section 2 “Sensorless control methods”, we have described 2 main sensorless

control methods which the ST7MC is compatible with. Please refer to AN1946 for more de-

tails. The steps to correctly configure the ST7MC registers depending on the sensorless con-

trol method used are as follows:

– Generate a Pulse Width Modulation signal. If the ST sensorless control method is used, then

a 2.5µs minimum off time is needed to read the BEMF voltage during the off time (useless in

Classic method detection).

In Voltage mode (the VOC1 bit is reset in the MCRA register), when driving a PM BLDC motor

(the PCN bit is reset in the MDTG register) in six-step drive, a single PWM signal is used to

supply the input stage. This PWM signal which is applied to the switches is generated using

the 12-bit PWM counter for frequency and the 13 bit compare U register for duty cycle

(MCPUL:MCPUH registers).

In Current mode (VOC1 bit is set in the MCRA register), the PWM output signal is generated

by a combination of the output of the measurement window generator and the output of the

current comparator and is directed to the output channel manager as well. This can be done

by setting the PWM frequency through SA[3:0] bits in the MPRSR register and the minimum

off time using the OT[3:0] bits in the MPWME register. The off time is also dependent on the

output of the current comparator as explained in Section 4 of this document.

– Apply this PWM on the high side or low side switches depending on the sensorless control

method used. To do so, you have to configure the microcontroller with the right configuration.

In order to configure correctly the registers, this sequence has to be followed.

– Split the switches in two parts by means of the high side/low side configuration. This is done

using the OE [5:0] bits in the MPAR register.

PARITY REGISTER (MPAR)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 5:0 = OE[5:0]: Output Parity Mode.

0: Output channel is High

1: Output channel Low

For example: T1, T3, T5 low side and T0, T2, T4 high side.

OE5

OE4

OE3

OE2

OE1

OE0

AN2009 Datasheet(PDF) 22 Page - STMicroelectronics