AN2009 datasheet(25/39 Pages) STMICROELECTRONICS

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PWM MANAGEMENT FOR 3-PHASE BLDC MOTOR DRIVES USING THE ST7MC

6 SYNCHRONOUS RECTIFICATION

6.1 SYNCHRONOUS RECTIFICATION PRINCIPLE

Whatever method is used, the classic method or the ST method, as soon as a PWM signal is

logically ANDed with the switch control signal, the free wheeling diodes of the triple half bridge

configuration are used during the off time off the PWM signal and the current continues to flow

in the same direction in the motor. The ST7MC features a dead time generator that allows ap-

plication of complementary PWM on the switch adjacent to the one where PWM is applied.

With this feature, the conduction losses can be reduced. This is called the “synchronous rec-

tification”.

Precautions must be taken to avoid short circuits in half bridges. This is ensured by driving

high and low side switches with complementary signals and by managing the time between

the switching-off and the switching-on instants of the adjacent switches. This time is the dead-

time and has to be adjusted depending on the devices connected to the PWM outputs and

their characteristics (intrinsic delays of level-shifters, delays due to power switches,...).

In the ST7MC, the dead time is set on six dedicated bits in a register allowing a range of dead

times from 125ns to 16µs. When Fmtc is 16MHz. Dead time can be set with steps of 125, 250

or 500ns.

As an example on Figure 14, if the dead time generator is activated, then during the off time of

the PWM on T3, T0 will be switched-on so the current will flow through the switch and not

through the free-wheeling diode D0.

Figure 15 shows the relationship between the output signals of the deadtime register on the

adjacent switches and its inputs.

Once activated, the dead time generator generates two output signals on the adjacent

switches: A and B.

The A output signal is the same as the input phase signal except for the rising edge, which is

delayed relative to the input signal rising edge.

The B output signal is the opposite of the input phase signal except the rising edge which is

delayed relative to the input signal falling edge.

AN2009 Datasheet(PDF) 25 Page - STMicroelectronics