AN2593

Spurious VIC interrupts

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Spurious VIC interrupts

4.1

Definition

Spurious interrupts are a characteristic of the VIC. This is due to the pipelined architecture

of the ARM core.

We know that when an interrupt occurs and it has the highest priority level, the VIC signals

an IRQ interrupt to the CPU and the VIC0 vector address register is loaded with the ISR

address.

Now suppose that just after having asserted the IRQ signal to the CPU, due to certain root

causes which are explained in the next section (Section 4.2), the interrupt source to VIC is

cleared, then in this case the VIC0 vector address register won’t be loaded with the ISR

address because the interrupt source was cleared in VIC. Instead, a default value is loaded

from the Defaut Vector Address register VIC0_DVAR.

So consequently the CPU will then jump to the default vector instead of the interrupt ISR

address: this is what we call “Spurious Interrupt”.

4.2

Root causes and handling of spurious interrupts

The reason why an interrupt in VIC could get cleared before being serviced is the fact that

CPU continues to executes some code in the pipeline before servicing the interrupt, and this

code in the pipeline could either:

1.

Clear the interrupt flag in the peripheral, so the interrupt is no longer asserted to the

VIC

2.

The code in the ARM pipeline disables the interrupt in the VIC

Note:

The reset value of the VIC0 Default Vector Address register is 0x0 so when a spurious

interrupt occurs the CPU will jump to address 0x0, which gives a surprising RESET-like

behavior.

In some applications, you can not avoid the possiblility of spurious interrupts occurring.

An example of this, is when you are working on peripherals with FIFO support like UART, in

these peripherals, the FIFO receive/transmit interrupt flags may be cleared simply by a

read/write in the FIFO, so it could be possible that an interrupt has been signalled to the VIC

but you have executed some code in pipeline which accessed the FIFO.

In order to avoid the surprising reset-like behaviour, it is important to assign a dummy

handler to the Default vector address registers of VIC0 and VIC1.

VIC0->DVAR = (u32)Dummy_Handler;

VIC1->DVAR = (u32)Dummy_Handler;

In this dummy handler just write any value to VIC0 and VIC1 vector address registers.

void Dummy_Handler(void)

{

VIC0->VAR = 0xFF;

VIC1->VAR = 0XFF;

}