Introduction to ST10F269Zx 0.35 µm embedded Flash memory

AN2692

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Flash commands and ST10 pipeline effect

Due to the ST10F269Zx pipeline effect, all erase and program commands must not be

immediately followed by a JMPx, CALLx or RETx instruction.

For any erase or program command, a NOP instruction must be inserted after sending the

last command to the Flash memory Erase/Program Controller.

When not implemented, and when the ST10F269Zx is in bootstrap mode with the code

running from the XRAM or an external memory, the TestFlash may be selected instead of

the user Flash memory (for details, please refer to ST10F269Zx errata sheet).

Read Protection

Status

RP

4

Addr.(2)

x2A54h

x15A8h x2A54h

Any odd word

address (5)

Read Protection Register

until a new write cycle is

initiated.

Data

xxA8h

xx54h

xx90h

Read PR

Block Temporary

Unprotection

BTU

4

Addr.(2)

x2A54h

x15A8h x2A54h

X

Data

xxA8h

xx54h

xxC1h

xxF0h

Code Temporary

Unprotection

CTU

1

Addr.(2)

Write cycles must be executed from Flash.

Data

FFFFh

Code Temporary

Protection

CTP

1

Addr.(2)

MEM (7)

Write cycles must be executed from Flash.

Data

FFFBh

1.

Mne = mnemonic, X = Don’t Care.

WA = Write Address: address of memory location to be programmed.

WD = Write Data: 16-bit data to be programmed.

BA = Block address.

2.

Address bit A14, A15 and above are don’t care for coded address inputs.

3.

Optional, additional blocks addresses must be entered within a timeout delay (96 µs) after last write entry, timeout status

can be verified through FSB.3 value. When full command is entered, read Data Polling or Toggle bit until Erase is

completed or suspended.

4.

Read data polling or toggle bit until erase completes.

5.

Odd word address = 4n-2 where n = 0, 1, 2, 3..., e.g. 0002h, 0006h, etc.

6.

WPR = Write protection register. To protect code, bit 15 of WPR must be ‘0’. To protect block N (N=0,1,...), bit N of WPR

must be ‘0’. Bit that are already at ‘0’ in protection register must also be ‘0’ in WPR, else a writing error will occurs (it is not

possible to write a ‘1’ in a bit already programmed at ‘0’).

7.

MEM = any address inside the Flash memory space. Absolute addressing mode must be used (MOV MEM, Rn), and

instruction must be executed from Flash memory space.

Table 1.

Instruction

Mne Cycle

Address/

Data

cycle

cycle

cycle

cycle

cycle

cycle