DocID17035 Rev 3

11/25

AN3147

Clock management

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3.3

Clock configuration and power management

In addition to the flexibility of the clock sources, different complementary clock

configurations and features are available to optimize the power consumption of the device:



Each peripheral clock can be switched on/off through the CLK_PCKENRx registers.



System clock divider from 1 to 8 (HSIDIV[1:0] bits in the CLK_CKDIVR register) is

available on STM8L101xx devices.



System clock divider from 1 to 128 (CKM[2:0] bits in the CLK_CKDIVR register) is

available on STM8L05xxx, STM8L15xxx, STM8L162xx, STM8AL31xx and

STM8AL3Lxx devices.

Note:

System clocks are used to supply both CPU and peripherals.

The STM8L and STM8AL devices are focused on low consumption. This is why all

peripheral clocks are gated by default. Before accessing any peripheral register, it is

mandatory to enable the clock for the given peripheral.

3.4

Clock selection vs. power consumption

The selected clock type and speed is one of the major factors influencing power

consumption of the MCU. In general, there are two parts in consumptions:



A static part, depending on the number of enabled peripherals (mainly analog ones)



A dynamic part, directly proportional to clock speed (increasing with higher clock

speed)

Note:

The values given above are measured with all peripherals disabled.

Slowing down the clock decreases the immediate consumption but this is not the ideal

solution in many cases. By slowing down the clock, the CPU performance is also reduced.

Therefore, a longer time is required to perform an action or computation. If we consider the

average consumption, it might be better to use the highest available clock speed to perform

the required operation, and force the MCU to one of the low power modes (like Active-halt

mode) for the remaining time frame. This should be taken into account during the design of

application flowcharts.



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+

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STM8L101xx



f 150 mA MHz

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

215 mA

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=