Run and low power modes

AN3147

18/25

DocID17035 Rev 3

4.8

Low power wait mode

This mode is entered by executing a WFE instruction, while the MCU is in Low power run

mode. It can be exited only by means of an external or internal event, in this case the MCU

returns to Low power run mode. WFI instruction cannot be used, because interrupts have to

be disabled in Low power run mode.

4.9

Halt mode

In this mode the system clock is stopped. This means that the CPU and all the peripherals

requiring clocks are disabled, except for the following cases:



The HSI clock is not stopped if used by the SWIM



The system clock source is not stopped if a Flash/Data EEPROM write operation is in

progress.



The LSI clock is not stopped if used by the SWIM, by the IWDG or if the “IWDG_HALT”

option bit is disabled.

In Halt mode, none of the peripherals is clocked and the digital part of the MCU consumes

almost no power.

4.9.1

Entering Halt mode

The MCU enters Halt mode when a HALT instruction is executed. Before executing a HALT

instruction, the application must clear any pending peripheral interrupt by clearing the

interrupt pending bit in the corresponding peripheral configuration register. Otherwise, the

HALT instruction is executed but the MCU wakes up immediately and the program

execution continues.

However, the Halt procedure can be delayed if one of the following flags is set:



SWBSY flag in the CLK_SWCR register



EEBUSY flag in the CLK_REGCSR register



RTCSWBSY flag in the CLK_CRTCR register



BEEPSWBSY flag in the CLK_CBEEPR register when the Beep is enabled in Active-

halt mode.

If the SAHALT bit is set in the CLK_ICKCR register, the main regulator (MVR) is switched off

without taking into account that some high speed clocks may be used by the system.