AN3422 datasheet(22/52 Pages) STMICROELECTRONICS

22 / 52 page

Peripheral migration

AN3422

22/52

Doc ID 018976 Rev 2

Table 7.

Example of migrating system clock configuration code from F1 to L1

STM32F105/7 running at 72 MHz (PLL as clock

source) with 2 wait states

STM32L1xx running at 22 MHz (PLL as clock source)

with 1 wait state

/* Enable HSE ----------------------------*/

RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Wait till HSE is ready */

while((RCC->CR & RCC_CR_HSERDY) == 0)

{

}

/* Flash configuration -------------------*/

/* Prefetch ON, Flash 2 wait states */

FLASH->ACR |= FLASH_ACR_PRFTBE |

FLASH_ACR_LATENCY_2;

/* AHB and APB prescaler configuration --*/

/* HCLK = SYSCLK */

RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK */

RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK */

RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;

/* PLL configuration -------------------*/

/* PLL2CLK = (HSE / 5) * 8 = 40 MHz

PREDIV1CLK = PLL2 / 5 = 8 MHz */

RCC->CFGR2 |= RCC_CFGR2_PREDIV2_DIV5 |

RCC_CFGR2_PLL2MUL8 |

RCC_CFGR2_PREDIV1SRC_PLL2 |

RCC_CFGR2_PREDIV1_DIV5;

/* Enable PLL2 */

RCC->CR |= RCC_CR_PLL2ON;

/* Wait till PLL2 is ready */

while((RCC->CR & RCC_CR_PLL2RDY) == 0)

{

}

/* PLLCLK = PREDIV1 * 9 = 72 MHz */

RCC->CFGR |= RCC_CFGR_PLLXTPRE_PREDIV1 |

RCC_CFGR_PLLSRC_PREDIV1 |

RCC_CFGR_PLLMULL9;

/* Enable the main PLL */

RCC->CR |= RCC_CR_PLLON;

/* Wait till the main PLL is ready */

while((RCC->CR & RCC_CR_PLLRDY) == 0)

{

}

/* Main PLL used as system clock source --*/

RCC->CFGR |= RCC_CFGR_SW_PLL;

/* Wait till the main PLL is used as system

clock source */

while ((RCC->CFGR & RCC_CFGR_SWS) !=

RCC_CFGR_SWS_PLL)

{

}

/* Enable HSE ----------------------------*/

RCC->CR |= ((uint32_t)RCC_CR_HSEON);

/* Wait till HSE is ready */

while((RCC->CR & RCC_CR_HSERDY) == 0)

{

}

/* Flash configuration -------------------*/

/* Flash prefetch and 64-bit access ON, Flash 1 wait

state */

FLASH->ACR |= FLASH_ACR_ACC64;

FLASH->ACR |= FLASH_ACR_PRFTEN;

FLASH->ACR |= FLASH_ACR_LATENCY;

/* Power enable */

RCC->APB1ENR |= RCC_APB1ENR_PWREN;

/* Select the Voltage Range 1 (1.8 V) */

PWR->CR = PWR_CR_VOS_0;

/* Wait Until the Voltage Regulator is ready */

while((PWR->CSR & PWR_CSR_VOSF) != RESET)

{

}

/* AHB and APB prescaler configuration --*/

/* HCLK = SYSCLK */

RCC->CFGR |= RCC_CFGR_HPRE_DIV1;

/* PCLK2 = HCLK / 1*/

RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

/* PCLK1 = HCLK / 1*/

RCC->CFGR |= RCC_CFGR_PPRE1_DIV1;

/* PLL configuration ---------------------*/

PLLCLK = (HSE * PLL_MUL) / PLL_DIV

= (8 MHz * 12) / 3

= 32MHz */

RCC->CFGR = RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12

| RCC_CFGR_PLLDIV3;

/* Enable the main PLL */

RCC->CR |= RCC_CR_PLLON;

/* Wait till the main PLL is ready */

while((RCC->CR & RCC_CR_PLLRDY) == 0)

{

}

/* Main PLL used as system clock source --*/

RCC->CFGR |= RCC_CFGR_SW_PLL;

/* Wait till the main PLL is used as system

clock source */

while ((RCC->CFGR & RCC_CFGR_SWS ) !=

RCC_CFGR_SWS_PLL);

{

}

AN3422 Datasheet(PDF) 22 Page - STMicroelectronics

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