PM0020 datasheet(32/87 Pages) STMICROELECTRONICS

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STR91xFA Flash memory

PM00020

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1.13.6

Flash configuration register

This register can be read using the RSIG command (see Section 1.11.2). It can be written

using the CR command (see Section 1.12.4). Reserved bit values cannot be modified. .The

(external or watchdog reset) will not change the register value).

987

6543210

Reserved

WSTATES[1:0]

PWD

LVD EN

reserved

BUS

CFG

reserved

Bits 15:13

Reserved, default value =001b.

Bits 12:11

WSTATES[1:0]: Wait states.

These bits define the number of wait states inserted in asynchronous read

accesses.

00: 1 Wait state (default)

01: 2 Wait states

10: 3 Wait states

Note: Wait States are inserted only for non-bursting Flash read bus cycles. One

wait state is required for a FMI bus clock frequency of 66 MHz or less. Two wait

states are required for 75 MHz bus clock frequency.

Bit 10

PWD: Power-down configuration.

0: Power-down disabled

1: Power-down enabled (default)

Bit 9

LVDEN: Low Voltage Detector enable.

This bit indicates if the LVD (reset and early warning interrupt) is disabled

0: LVD enabled (default)

1: LVD disabled

Bits 8:5

Reserved, default value = 0110b

Bit 4

BUSCFG: Flash bus clock configuration.

This bit selects the FMI Flash bus clock configuration. It can be set by software

to configure the bus for frequencies greater than 66 MHz.

0: Low frequency bus clock (default)

1: Bus clock speed > 66 MHz

Bits 3:0

Reserved, default value =1111b.

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