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PM0020 Datasheet(PDF) 37 Page - STMicroelectronics |
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PM0020 Datasheet(HTML) 37 Page - STMicroelectronics |
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37 / 87 page  PM00020 STR91xFA Flash memory 37/87 1.15.4 Non-boot bank base address register (FMI_NBBADR) Address Offset: 5400 0010h Reset value: 0000 0000h 1.15.5 FMI control register (FMI_CR) Address Offset: 5400 0018h Reset value: 0000 0008h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved NBBADDR[23:16] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9876543210 NBBADDR[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, always read as 0 Bits 23:0 NBBADDR[23:0]: Non-boot bank base address These bits are set and cleared by software. They define the base address of the non- boot bank. The Flash Bank address NBBADDR[23:0] is a word address and is mapped to CPU core address A[25:2]. The Non-boot bank base address must be at a Non-boot bank size boundary. Example (STR91xFAxx4) : at 32KB boundary for Bank1 and for Bank 0, it must be at a 512KB boundary. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WWS OMIE BEIE Res. NBB EN BBEN Reserved rw rw rw rw rw rw Bits 31:9 Reserved, always read as 0 Bit 8 WWS: Write Wait States This bit is set and cleared by software. It defines the number of wait states in Flash write access. 0: Flash write is active for 1 clock cycle (Recommended setting) 1: Flash write is active for 2 clock cycles (Reserved for future use) Bit 7 OMIE: Out of Memory interrupt enable This bit is set and cleared by software. It enables/disables the Out of Memory interrupts. 0: Disabled 1: Enabled. An interrupt is generated when the OM bit in the FMI_SR register is set. Bit 6 BERRIE: Flash Bank Error interrupt enable This bit is set and cleared by software. It enables/disables Flash bank error interrupts. 0: Disabled 1: Enabled. An interrupt is generated when the B1ERR or B0ERR bit in the FMI_SR register are set. |
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