PM0068 datasheet(27/31 Pages) STMICROELECTRONICS

27 / 31 page

PM0068

Doc ID 17100 Rev 2

27/31

3.11

Flash control register2 (FLASH_CR2)

This register is dedicated to Flash memory bank 2.

Address offset: 0x50

Reset value: 0x0000 0080

Reserved

EOPIE

Res.

ERRIE

Reserved

LOCK

STRT

Reserved

MER

PER

Bits 31:13 Reserved, must be kept cleared.

Bit 12 EOPIE: End of operation interrupt enable

This bit enables the interrupt generation when the EOP bit in the FLASH_SR2 register goes

to 1.

0: Interrupt generation disabled

1: Interrupt generation enabled

Bit 11 Reserved, must be kept cleared

Bit 10 ERRIE: Error interrupt enable

This bit enables the interrupt generation on an FPEC error (when PGERR / WRPRTERR are

set in the FLASH_SR2 register).

0: Interrupt generation disabled

1: Interrupt generation enabled

Bit 9 Reserved, must be kept cleared.

Bit 8 Reserved, must be kept cleared.

Bit 7 LOCK: Lock

Write to 1 only. When it is set, it indicates that the FPEC and FLASH_CR2 are locked. This

bit is reset by hardware after detecting the unlock sequence.

In the event of unsuccessful unlock operation, this bit remains set until the next reset.

Bit 6 STRT: Start

This bit triggers an ERASE operation when set. This bit is set only by software and reset

when the BSY bit is reset.

Bits 5:3 Reserved, must be kept cleared.

Bit 2 MER: Mass erase

Erase of all user pages selected.

Bit 1 PER: Page erase

Page Erase chosen.

Bit 0 PG: Programming

Flash programming selected.

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