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PM0073 Datasheet(PDF) 12 Page - STMicroelectronics |
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PM0073 Datasheet(HTML) 12 Page - STMicroelectronics |
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12 / 34 page  Reading/programming the STM32Wxxx embedded Flash memory PM0073 12/34 Doc ID 17766 Rev 5 2 Reading/programming the STM32Wxxx embedded Flash memory This section describes how to read from or program to the STM32Wxxx embedded Flash memory. 2.1 Read operation The embedded Flash module can be addressed directly, as a common memory space. Any data read operation accesses the content of the Flash module through dedicated read senses and provides the requested data. The read interface consists of a read controller on one side to access the Flash memory and an AHB interface on the other side to interface with the CPU. The main task of the read interface is to generate the control signals to read from the Flash memory and to prefetch the blocks required by the CPU. The prefetch block is only used for instruction fetches over the I-Code bus. The Literal pool is accessed over the D-Code bus. Since these two buses have the same Flash memory as target, D-code bus accesses have priority over prefetch accesses. 2.1.1 Instruction fetch The Cortex™-M3 core fetches the instruction over the I-Code bus and the literal pool (constant/data) over the D-code bus. The cache block aims at increasing the efficiency of the I-Code bus in terms of power consumption and overall access time. Cache buffer The device is provided with one line of a direct mapped cache (8 bytes wide). The cache stores the most recent instruction line read by the Flash memory. To optimize the power consumption and the overall CPU execution time, it is suggested to enable the cache by setting bit FLASH_ACR[4] to '1'. Any Flash instruction read access will provide two 32-bit wide instructions; the first one is directly read by the CPU and the second one will be stored into the cache making it available for the next CPU instruction request. Access time tuner In order to maintain the control signals to read the Flash memory, the ratio of the prefetch controller clock period to the access time of the Flash memory has to be programmed in the Flash access control register. This value gives the number of cycles needed to maintain the control signals of the Flash memory and correctly read the required data. After reset, the value is zero and only one cycle is required to access the Flash memory. 2.1.2 D-Code interface The D-Code interface consists of a simple AHB interface on the CPU side and a request generator to the Arbiter of the Flash access controller. D-code accesses have priority over prefetch accesses. This interface uses the Access Time Tuner block of the prefetch buffer. |
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