PM0073 datasheet(27/34 Pages) STMICROELECTRONICS

27 / 34 page

PM0073

Doc ID 17766 Rev 5

27/34

3.4

Flash status register (FLASH_SR)

Address offset: 0x0C

Reset value: 0x0000 0000

Reserved

EOP

WRPRT

ERR

Res.

ERR

Res.

BSY

Bits 31:6 Reserved, must be kept cleared.

Bit 5

EOP: End of operation

Set by hardware when a Flash operation (programming / erase) is completed. Reset by

writing 1.

Note: EOP is asserted at the end of each successful program or erase operation.

Bit 4

WRPRTERR: Write protection error

Set by hardware when programming a write-protected address of the Flash memory.

Reset by writing 1.

Bit 3 Reserved, must be kept cleared.

Bit 2

PGERR: Programming error

Set by hardware when an address to be programmed contains a value different from

'0xFFFF' before programming.

Reset by writing 1.

Note: The STRT bit in the FLASH_CR register should be reset before starting a programming

operation.

Bit 1 Reserved, must be kept cleared

Bit 0

BSY: Busy

This indicates that a Flash operation is in progress. This is set at the beginning of a Flash

operation and reset when the operation finishes or when an error occurs.

PM0073 Datasheet(PDF) 27 Page - STMicroelectronics